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[RFC,5/5] RISC-V: define ioremap_cache

Message ID 20250206131926.91289-6-qirui.001@bytedance.com
State New
Headers show
Series riscv: initial support for Generic Hardware Error Source (GHES) | expand

Commit Message

Rui Qi Feb. 6, 2025, 1:19 p.m. UTC 
From: Rui Qi <qirui.001@bytedance.com>

Define ioremap_cache for riscv, otherwise it will
cause compile errors for bert.c and einj.c

Signed-off-by: Rui Qi <qirui.001@bytedance.com>
---
 arch/riscv/include/asm/io.h | 5 +++++
 1 file changed, 5 insertions(+)
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Patch

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index 1c5c641075d2..c81d2de007bc 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -134,6 +134,11 @@  __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 #endif
 
 #include <asm-generic/io.h>
+#define ioremap_cache ioremap_cache
+static inline void __iomem *ioremap_cache(phys_addr_t addr, size_t size)
+{
+	return (__force void *)ioremap_prot(addr, size, _PAGE_KERNEL);
+}
 
 #ifdef CONFIG_MMU
 #define arch_memremap_wb(addr, size)	\