From patchwork Mon Jul 8 11:18:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 811267 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B46A79B99; Mon, 8 Jul 2024 11:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; cv=none; b=Ge8UloQQxdPN7YESdkNrCgSW4B43ehlMSVbXEHjst/Go5KIC9EFxe7e3w1em8UvEA+DFWq/K/8gbqplpuX/83mqLqfsZTYbdgwzMYM71O0rR/XZp4bKquUtr++KraQbA6Fdohfdt9iecmSaylpcWzr4Ow6U0dp5e8W1UJdYHYHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720437554; c=relaxed/simple; bh=JWDF3uYI/wZ37tgeaDZgy9qmXzyOCRUzF9V3nIAkQKQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=moceSbInNBpgSXTW7NEwEfODNlCxmYZ4v1v0LFh566sH6YPjEaXtAEn6WcR7PhI2rHTm7+26eVqhkDVvgs/NjLyynTyafnEtcxLpormoc9sRWiqKyxvdfP10c6fY+qKuFchLeNgtqF8WMvjkj9mfnd2uwzXJMAgf1mZAQ5GBvAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uqnjomc/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uqnjomc/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09B2BC4AF0E; Mon, 8 Jul 2024 11:19:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1720437554; bh=JWDF3uYI/wZ37tgeaDZgy9qmXzyOCRUzF9V3nIAkQKQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uqnjomc/HoOLZmpDetAlgAqPTNWzFNB5H6+GGvWxjZC09QQmeFEdWsmuZNS5P9og0 9usjO/l0OkjCZq5vy6mjtNI0X0pzy+bGlAfmosepEfwfQhvJRJQhMzLyYnGqwbrXLf azKPZQbACKqpyruGDAFMJbYGvl5/DBFhqc5T3SZUNQfahLZ8b0+s8hX0wGWog2ESVP l5Vrc3YvLIue6Yc8+Hjm/9VRWRIEDZcN8+tSmg97gKsy3lXXt2223+DqeSCelrhRs0 mBv4yZoGTWtwXCBL4mk8YD37kdBDVVWIFV1fHyH1/lXTM0Ssy0+KaJq4Y26Z7cFFds ShvBgtTqDvApA== Received: from mchehab by mail.kernel.org with local (Exim 4.97.1) (envelope-from ) id 1sQmOl-00000001SQZ-2GDO; Mon, 08 Jul 2024 13:19:11 +0200 From: Mauro Carvalho Chehab To: Borislav Petkov , Tony Luck Cc: Daniel Ferguson , "Ard Biesheuvel" , "James Morse" , "Jonathan Cameron" , "Len Brown" , "Rafael J. Wysocki" , "Shiju Jose" , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Dan Williams , Dave Jiang , Ira Weiny , Shuai Xue , linux-acpi@vger.kernel.org, linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, linux-kernel@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH 1/6] RAS: ACPI: APEI: add conditional compilation to ARM error report functions Date: Mon, 8 Jul 2024 13:18:10 +0200 Message-ID: X-Mailer: git-send-email 2.45.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab From: Daniel Ferguson This prevents the unnecessary inclusion of ARM specific RAS error handling routines in non-ARM platforms. [mchehab: avoid unneeded ifdefs and fix coding style issues] Signed-off-by: Daniel Ferguson Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Jonathan Cameron --- drivers/acpi/apei/ghes.c | 13 ++++++------- drivers/ras/ras.c | 2 ++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 623cc0cb4a65..2589a3536d91 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -529,11 +529,12 @@ static bool ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata, } static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, - int sev, bool sync) + int sev, bool sync) { + bool queued = false; +#if defined(CONFIG_ARM) || defined (CONFIG_ARM64) struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata); int flags = sync ? MF_ACTION_REQUIRED : 0; - bool queued = false; int sec_sev, i; char *p; @@ -570,7 +571,7 @@ static bool ghes_handle_arm_hw_error(struct acpi_hest_generic_data *gdata, error_type); p += err_info->length; } - +#endif return queued; } @@ -773,11 +774,9 @@ static bool ghes_do_proc(struct ghes *ghes, arch_apei_report_mem_error(sev, mem_err); queued = ghes_handle_memory_failure(gdata, sev, sync); - } - else if (guid_equal(sec_type, &CPER_SEC_PCIE)) { + } else if (guid_equal(sec_type, &CPER_SEC_PCIE)) { ghes_handle_aer(gdata); - } - else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { + } else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { queued = ghes_handle_arm_hw_error(gdata, sev, sync); } else if (guid_equal(sec_type, &CPER_SEC_CXL_GEN_MEDIA_GUID)) { struct cxl_cper_event_rec *rec = acpi_hest_get_payload(gdata); diff --git a/drivers/ras/ras.c b/drivers/ras/ras.c index a6e4792a1b2e..5d94ab79c8c3 100644 --- a/drivers/ras/ras.c +++ b/drivers/ras/ras.c @@ -54,7 +54,9 @@ void log_non_standard_event(const guid_t *sec_type, const guid_t *fru_id, void log_arm_hw_error(struct cper_sec_proc_arm *err) { +#if defined(CONFIG_ARM) || defined(CONFIG_ARM64) trace_arm_event(err); +#endif } static int __init ras_init(void)