From patchwork Mon Oct 5 08:28:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chia-Wei Wang X-Patchwork-Id: 267403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19D66C4363A for ; Mon, 5 Oct 2020 08:49:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DC72F2064C for ; Mon, 5 Oct 2020 08:49:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725984AbgJEIt4 (ORCPT ); Mon, 5 Oct 2020 04:49:56 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:46826 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725885AbgJEIt4 (ORCPT ); Mon, 5 Oct 2020 04:49:56 -0400 Received: from twspam01.aspeedtech.com (localhost [127.0.0.2] (may be forged)) by twspam01.aspeedtech.com with ESMTP id 09588de5047530 for ; Mon, 5 Oct 2020 16:08:39 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 09588T7v047497; Mon, 5 Oct 2020 16:08:29 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 5 Oct 2020 16:28:09 +0800 From: "Chia-Wei, Wang" To: , , , , , , , , , , , , , , , CC: Subject: [PATCH v2 0/5] Remove LPC register partitioning Date: Mon, 5 Oct 2020 16:28:01 +0800 Message-ID: <20201005082806.28899-1-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 09588T7v047497 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The LPC controller has no concept of the BMC and the Host partitions. The incorrect partitioning can impose unnecessary range restrictions on register access through the syscon regmap interface. For instance, HICRB contains the I/O port address configuration of KCS channel 1/2. However, the KCS#1/#2 drivers cannot access HICRB as it is located at the other LPC partition. In addition, to be backward compatible, the newly added HW control bits could be located at any reserved bits over the LPC addressing space. Thereby, this patch series aims to remove the LPC partitioning for better driver development and maintenance. Changes since v1: - Add the fix to the aspeed-lpc binding documentation. Chia-Wei, Wang (5): ARM: dts: Remove LPC BMC and Host partitions soc: aspeed: Fix LPC register offsets ipmi: kcs: aspeed: Fix LPC register offsets pinctrl: aspeed-g5: Fix LPC register offsets dt-bindings: aspeed-lpc: Remove LPC partitioning .../devicetree/bindings/mfd/aspeed-lpc.txt | 85 ++--------- arch/arm/boot/dts/aspeed-g4.dtsi | 74 ++++------ arch/arm/boot/dts/aspeed-g5.dtsi | 135 ++++++++---------- arch/arm/boot/dts/aspeed-g6.dtsi | 135 ++++++++---------- drivers/char/ipmi/kcs_bmc_aspeed.c | 13 +- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 6 +- drivers/soc/aspeed/aspeed-lpc-snoop.c | 11 +- 8 files changed, 176 insertions(+), 285 deletions(-)