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Thu, 5 Aug 2021 10:42:46 -0700 Envelope-to: git@xilinx.com, arnd@arndb.de, zou_wei@huawei.com, gregkh@linuxfoundation.org, linus.walleij@linaro.org, iwamatsu@nigauri.org, bgolaszewski@baylibre.com, robh+dt@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Received: from [10.140.6.35] (port=51088 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mBhOH-0005Bw-0L; Thu, 05 Aug 2021 10:42:45 -0700 From: Piyush Mehta To: , , , , , , , , , CC: , , , , , , Piyush Mehta Subject: [PATCH V2 0/3] gpio: modepin: Add driver support for modepin GPIO controller Date: Thu, 5 Aug 2021 23:12:16 +0530 Message-ID: <20210805174219.3000667-1-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: be715b52-313e-4461-5a71-08d9583874dc X-MS-TrafficTypeDiagnostic: PH0PR02MB7589: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:626; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(921005)(316002)(7416002)(44832011)(82310400003)(47076005)(6666004)(8676002)(186003)(2906002)(110136005)(107886003)(426003)(36860700001)(70586007)(83380400001)(2616005)(356005)(70206006)(1076003)(508600001)(9786002)(54906003)(4326008)(966005)(336012)(7636003)(5660300002)(36906005)(8936002)(26005)(7696005)(6636002)(36756003)(102446001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Aug 2021 17:42:55.0847 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be715b52-313e-4461-5a71-08d9583874dc X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0046.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR02MB7589 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds support for the zynqmp modepin GPIO controller and documented for the same. GPIO modepin driver set and get the value and status of the PS_MODE pin, based on device-tree pin configuration. These four-bits boot-mode pins are dedicated configurable as input/output. After the stabilization of the system,these mode pins are sampled. To access GPIO pins, added Xilinx ZynqMP firmware MDIO API support to set and get PS_MODE pins value and status. These APIs are interface APIs, between the mode pin controller driver and low-level API. --- Changes in v2: - Added Xilinx ZynqMP firmware MMIO API support to set and get pin value and status. - DT Documentation- Addressed review comments: Update commit message - Modepin driver- Addressed review comments: - Update APIs - Removed unwanted variables - Handle return path for probe function Review Comments: https://lore.kernel.org/linux-arm-kernel/20210624205055.GA1961487@robh.at.kernel.org/T/#u --- Piyush Mehta (3): firmware: zynqmp: Add MMIO read and write support for PS_MODE pin dt-bindings: gpio: zynqmp: Add binding documentation for modepin gpio: modepin: Add driver support for modepin GPIO controller .../bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 41 ++++++ drivers/firmware/xilinx/zynqmp.c | 46 ++++++ drivers/gpio/Kconfig | 12 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-zynqmp-modepin.c | 158 +++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 14 ++ 6 files changed, 272 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml create mode 100644 drivers/gpio/gpio-zynqmp-modepin.c