[00/13] Update the icicle kit device tree

From: Conor Dooley <conor.dooley@microchip.com>

This series updates the microchip icicle kit device tree by adding a host
of peripherals, and some updates to the memory map. In addition, the device
tree has been split into a third part, which contains "soft" peripherals 
that are in the fpga fabric.

Several of the entries are for peripherals that have not get had their drivers
upstreamed, so in those cases the dt bindings are included where appropriate
in order to avoid as many "DT compatible string <x> appears un-documented" 
errors as possible.

Depends on mpfs clock driver series [1] to provide:
dt-bindings/clock/microchip,mpfs-clock.h
and on the other changes to the icicle/mpfs device tree
that are already in linux/riscv/for-next.

[1] https://lore.kernel.org/linux-clk/20210818141102.36655-2-daire.mcnamara@microchip.com/

Conor Dooley (11):
  dt-bindings: soc/microchip: update sys ctrlr compat string
  dt-bindings: riscv: update microchip polarfire binds
  dt-bindings: i2c: add bindings for microchip mpfs i2c
  dt-bindings: rng: add bindings for microchip mpfs rng
  dt-bindings: rtc: add bindings for microchip mpfs rtc
  dt-bindings: soc/microchip: add bindings for mpfs system services
  dt-bindings: gpio: add bindings for microchip mpfs gpio
  dt-bindings: spi: add bindings for microchip mpfs spi
  dt-bindings: usb: add bindings for microchip mpfs musb
  riscv: icicle-kit: update microchip icicle kit device tree
  MAINTAINERS: update riscv/microchip entry

Ivan Griffin (2):
  dt-bindings: interrupt-controller: add defines for riscv-hart
  dt-bindings: interrupt-controller: add defines for mpfs-plic

 .../bindings/gpio/microchip,mpfs-gpio.yaml    | 108 ++++++
 .../bindings/i2c/microchip,mpfs-i2c.yaml      |  74 ++++
 .../microchip,polarfire-soc-mailbox.yaml      |   4 +-
 .../devicetree/bindings/riscv/microchip.yaml  |   1 +
 .../bindings/rng/microchip,mpfs-rng.yaml      |  31 ++
 .../bindings/rtc/microchip,mfps-rtc.yaml      |  61 ++++
 .../microchip,mpfs-generic-service.yaml       |  31 ++
 ...icrochip,polarfire-soc-sys-controller.yaml |   4 +-
 .../bindings/spi/microchip,mpfs-spi.yaml      |  72 ++++
 .../bindings/usb/microchip,mpfs-usb-host.yaml |  70 ++++
 MAINTAINERS                                   |   2 +
 .../dts/microchip/microchip-mpfs-fabric.dtsi  |  21 ++
 .../microchip/microchip-mpfs-icicle-kit.dts   | 159 +++++++--
 .../boot/dts/microchip/microchip-mpfs.dtsi    | 333 ++++++++++++++----
 drivers/mailbox/mailbox-mpfs.c                |   1 +
 .../microchip,mpfs-plic.h                     | 199 +++++++++++
 .../interrupt-controller/riscv-hart.h         |  19 +
 17 files changed, 1103 insertions(+), 87 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
 create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
 create mode 100644 Documentation/devicetree/bindings/rng/microchip,mpfs-rng.yaml
 create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-generic-service.yaml
 create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
 create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-usb-host.yaml
 create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
 create mode 100644 include/dt-bindings/interrupt-controller/microchip,mpfs-plic.h
 create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h

Am Montag, 8. November 2021, 16:05:42 CET schrieb conor.dooley@microchip.com:
> From: Ivan Griffin <ivan.griffin@microchip.com>
> 
> Provide named identifiers for device tree for RISC-V interrupts.
> 
> Licensed under GPL and MIT, as this file may be useful to any OS that
> uses device tree.
> 
> Signed-off-by: Ivan Griffin <ivan.griffin@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../interrupt-controller/riscv-hart.h         | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
> 
> diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
> new file mode 100644
> index 000000000000..e1c32f6090ac
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2021 Microchip Technology Inc.  All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +
> +#define HART_INT_U_SOFT   0
> +#define HART_INT_S_SOFT   1
> +#define HART_INT_M_SOFT   3
> +#define HART_INT_U_TIMER  4
> +#define HART_INT_S_TIMER  5
> +#define HART_INT_M_TIMER  7
> +#define HART_INT_U_EXT    8
> +#define HART_INT_S_EXT    9
> +#define HART_INT_M_EXT    11

(1) From checking clic doc [0] I see an additional
	12   CLIC software interrupt
defined.

(2) The doc states that the ordering is a recommendation and
	"not mandatory in all incarnations of the CLIC"
Is that clarified somewhere else that this more than recommended?

Thanks
Heiko


[0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc

> +
> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
>

On Mon, Nov 08, 2021 at 03:05:44PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Update 'compatible' strings for system controller drivers to the
> approved Microchip name.

Why do I care what Microchip approved? You all picked identifiers 
(that's all it is) and now get to live with them.

> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../bindings/mailbox/microchip,polarfire-soc-mailbox.yaml     | 4 +++-
>  .../soc/microchip/microchip,polarfire-soc-sys-controller.yaml | 4 +++-
>  drivers/mailbox/mailbox-mpfs.c                                | 1 +
>  3 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> index bbb173ea483c..b08c8a158eea 100644
> --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> @@ -11,7 +11,9 @@ maintainers:
>  
>  properties:
>    compatible:
> -    const: microchip,polarfire-soc-mailbox
> +    enum:
> +      - microchip,polarfire-soc-mailbox
> +      - microchip,mpfs-mailbox
>  
>    reg:
>      items:
> diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> index 2cd3bc6bd8d6..d6c953cd154b 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
> @@ -19,7 +19,9 @@ properties:
>      maxItems: 1
>  
>    compatible:
> -    const: microchip,polarfire-soc-sys-controller
> +    enum:
> +      - microchip,polarfire-soc-sys-controller
> +      - microchip,mpfs-sys-controller
>  
>  required:
>    - compatible
> diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
> index 0d6e2231a2c7..9d5e558a6ee6 100644
> --- a/drivers/mailbox/mailbox-mpfs.c
> +++ b/drivers/mailbox/mailbox-mpfs.c
> @@ -233,6 +233,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev)
>  
>  static const struct of_device_id mpfs_mbox_of_match[] = {
>  	{.compatible = "microchip,polarfire-soc-mailbox", },
> +	{.compatible = "microchip,mpfs-mailbox", },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
> -- 
> 2.33.1
> 
>