| Message ID | 20220214135840.168236-1-conor.dooley@microchip.com |
|---|---|
| Headers | show |
| Series | Update the Icicle Kit device tree | expand |
Hey Uwe, Could you take a look at this version & see if the descriptions are easier to understand? Thanks, Conor On 14/02/2022 13:58, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the Microchip fpga fabric based "core" PWM > controller. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > --- > .../bindings/pwm/microchip,corepwm.yaml | 81 +++++++++++++++++++ > 1 file changed, 81 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml > new file mode 100644 > index 000000000000..a7fae1772a81 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip IP corePWM controller bindings > + > +maintainers: > + - Conor Dooley <conor.dooley@microchip.com> > + > +description: | > + corePWM is an 16 channel pulse width modulator FPGA IP > + > + https://www.microsemi.com/existing-parts/parts/152118 > + > +allOf: > + - $ref: pwm.yaml# > + > +properties: > + compatible: > + items: > + - const: microchip,corepwm-rtl-v4 > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + "#pwm-cells": > + const: 2 > + > + microchip,sync-update-mask: > + description: | > + Depending on how the IP is instantiated, there are two modes of operation. > + In synchronous mode, all channels are updated at the beginning of the PWM period, > + and in asynchronous mode updates happen as the control registers are written. > + A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous > + mode is possible for each channel, and is set by the bitstream programmed to the > + FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that > + control the duty cycle for channel x have a second "shadow"/buffer reg synthesised. > + At runtime a bit wide register exposed to APB can be used to toggle on/off > + synchronised mode for all channels it has been synthesised for. > + Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents > + whether synchronous mode is possible for the PWM channel. > + > + $ref: /schemas/types.yaml#/definitions/uint32 > + default: 0 > + > + microchip,dac-mode-mask: > + description: | > + Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates > + a minimum period pulse train whose High/Low average is that of the chosen duty > + cycle. This "DAC" will have far better bandwidth and ripple performance than the > + standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP > + core, set at instantiation and by the bitstream programmed to the FPGA, determines > + whether a given channel operates in regular PWM or DAC mode. > + Each bit corresponds to a PWM channel & represents whether DAC mode is enabled > + for that channel. > + > + $ref: /schemas/types.yaml#/definitions/uint32 > + default: 0 > + > +required: > + - compatible > + - reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + pwm@41000000 { > + compatible = "microchip,corepwm-rtl-v4"; > + microchip,sync-update-mask = /bits/ 32 <0>; > + clocks = <&clkcfg 30>; > + reg = <0x41000000 0xF0>; > + #pwm-cells = <2>; > + };
On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the Microchip fpga fabric based "core" PWM > controller. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> I like it: Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> nitpick: Put your S-o-b last in the commit log. (This doesn't justify a resend IMHO) Best regards Uwe
On 23/02/2022 07:20, Uwe Kleine-König wrote: > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Add device tree bindings for the Microchip fpga fabric based "core" PWM >> controller. >> >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > I like it: > > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> > > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a > resend IMHO) It should be the opposite - the first. First author signs the patch, then comes review and finally an ack. Putting SoB at then suggests that tags were accumulated before sending patch, out of mailing list. Best regards, Krzysztof
Hi Alessandro, Alexandre, If one of you could take a look at this, that'd be great. Thanks, Conor. On 14/02/2022 13:58, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the real time clock on > the Microchip PolarFire SoC. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > Reviewed-by: Rob Herring <robh@kernel.org> > --- > .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++ > 1 file changed, 58 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > > diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > new file mode 100644 > index 000000000000..a2e984ea3553 > --- /dev/null > +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > @@ -0,0 +1,58 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# > + > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings > + > +allOf: > + - $ref: rtc.yaml# > + > +maintainers: > + - Daire McNamara <daire.mcnamara@microchip.com> > + - Lewis Hanly <lewis.hanly@microchip.com> > + > +properties: > + compatible: > + enum: > + - microchip,mpfs-rtc > + > + reg: > + maxItems: 1 > + > + interrupts: > + items: > + - description: | > + RTC_WAKEUP interrupt > + - description: | > + RTC_MATCH, asserted when the content of the Alarm register is equal > + to that of the RTC's count register. > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: rtc > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + rtc@20124000 { > + compatible = "microchip,mpfs-rtc"; > + reg = <0x20124000 0x1000>; > + clocks = <&clkcfg 21>; > + clock-names = "rtc"; > + interrupts = <80>, <81>; > + }; > +...
On Wed, 23 Feb 2022, Uwe Kleine-König wrote: > On Wed, Feb 23, 2022 at 08:12:49AM +0100, Krzysztof Kozlowski wrote: > > On 23/02/2022 07:20, Uwe Kleine-König wrote: > > > On Mon, Feb 14, 2022 at 01:58:35PM +0000, conor.dooley@microchip.com wrote: > > >> From: Conor Dooley <conor.dooley@microchip.com> > > >> > > >> Add device tree bindings for the Microchip fpga fabric based "core" PWM > > >> controller. > > >> > > >> Reviewed-by: Rob Herring <robh@kernel.org> > > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > > > > > I like it: > > > > > > Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> > > > > > > nitpick: Put your S-o-b last in the commit log. (This doesn't justify a > > > resend IMHO) > > > > It should be the opposite - the first. First author signs the patch, > > then comes review and finally an ack. Putting SoB at then suggests that > > tags were accumulated before sending patch, out of mailing list. > > well, or in an earlier revision of this patch as is the case here. One > of the ideas of S-o-b is that the order shows the flow of the patch > states and if this patch ends in git with: > > Referred-by: Rob Herring <robh@kernel.org> > Singed-off-by: Conor Dooley <conor.dooley@microchip.com> > Backed-by: Palmer Dabbelt <palmer@rivosinc.com> > Singed-off-by: Peter Maintainer <pm@example.com> > > I'd expect that Backed-by was added by Peter, not Conor. > (Modified the tags on purpose to not interfere with b4's tag pickup, I > guess you humans still get the point.) I tend to like *-by tags to appear chronologically. Suggested (suggested-by) Authored (signed-off-by) Co-Authored (signed-off-by/co-developed-by) Reviewed/Acked/Tested (reviewed-by/acked-by/tested-by) Committed (signed-off-by)
On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote: > Hi Alessandro, Alexandre, > If one of you could take a look at this, that'd be great. I actually expected someone else to apply this, what is your plan? > Thanks, > Conor. > > On 14/02/2022 13:58, conor.dooley@microchip.com wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > > > Add device tree bindings for the real time clock on > > the Microchip PolarFire SoC. > > > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++ > > 1 file changed, 58 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > > > > diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > > new file mode 100644 > > index 000000000000..a2e984ea3553 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml > > @@ -0,0 +1,58 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# > > + > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings > > + > > +allOf: > > + - $ref: rtc.yaml# > > + > > +maintainers: > > + - Daire McNamara <daire.mcnamara@microchip.com> > > + - Lewis Hanly <lewis.hanly@microchip.com> > > + > > +properties: > > + compatible: > > + enum: > > + - microchip,mpfs-rtc > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + items: > > + - description: | > > + RTC_WAKEUP interrupt > > + - description: | > > + RTC_MATCH, asserted when the content of the Alarm register is equal > > + to that of the RTC's count register. > > + > > + clocks: > > + maxItems: 1 > > + > > + clock-names: > > + items: > > + - const: rtc > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + - clock-names > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + rtc@20124000 { > > + compatible = "microchip,mpfs-rtc"; > > + reg = <0x20124000 0x1000>; > > + clocks = <&clkcfg 21>; > > + clock-names = "rtc"; > > + interrupts = <80>, <81>; > > + }; > > +... >
On 23/02/2022 20:20, Alexandre Belloni wrote: > On 23/02/2022 15:25:00+0000, Conor.Dooley@microchip.com wrote: >> On 23/02/2022 15:18, Alexandre Belloni wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> On 23/02/2022 07:41:27+0000, Conor.Dooley@microchip.com wrote: >>>> Hi Alessandro, Alexandre, >>>> If one of you could take a look at this, that'd be great. >>> >>> I actually expected someone else to apply this, what is your plan? >> >> I was going to ask Palmer to take the series via riscv. Since I have >> Rob's R-b, I was just looking for a subsystem maintainer ack/R-b before >> actually asking him. >> > > Rob's review is enough for a DT binding, no need to wait for me. but > FWIW: > > Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Great, thanks. > > >> Thanks, >> Conor. >> >>> >>>> Thanks, >>>> Conor. >>>> >>>> On 14/02/2022 13:58, conor.dooley@microchip.com wrote: >>>>> From: Conor Dooley <conor.dooley@microchip.com> >>>>> >>>>> Add device tree bindings for the real time clock on >>>>> the Microchip PolarFire SoC. >>>>> >>>>> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> >>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >>>>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> >>>>> Reviewed-by: Rob Herring <robh@kernel.org> >>>>> --- >>>>> .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++ >>>>> 1 file changed, 58 insertions(+) >>>>> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml >>>>> new file mode 100644 >>>>> index 000000000000..a2e984ea3553 >>>>> --- /dev/null >>>>> +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml >>>>> @@ -0,0 +1,58 @@ >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>> +%YAML 1.2 >>>>> +--- >>>>> +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# >>>>> + >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>> + >>>>> +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings >>>>> + >>>>> +allOf: >>>>> + - $ref: rtc.yaml# >>>>> + >>>>> +maintainers: >>>>> + - Daire McNamara <daire.mcnamara@microchip.com> >>>>> + - Lewis Hanly <lewis.hanly@microchip.com> >>>>> + >>>>> +properties: >>>>> + compatible: >>>>> + enum: >>>>> + - microchip,mpfs-rtc >>>>> + >>>>> + reg: >>>>> + maxItems: 1 >>>>> + >>>>> + interrupts: >>>>> + items: >>>>> + - description: | >>>>> + RTC_WAKEUP interrupt >>>>> + - description: | >>>>> + RTC_MATCH, asserted when the content of the Alarm register is equal >>>>> + to that of the RTC's count register. >>>>> + >>>>> + clocks: >>>>> + maxItems: 1 >>>>> + >>>>> + clock-names: >>>>> + items: >>>>> + - const: rtc >>>>> + >>>>> +required: >>>>> + - compatible >>>>> + - reg >>>>> + - interrupts >>>>> + - clocks >>>>> + - clock-names >>>>> + >>>>> +additionalProperties: false >>>>> + >>>>> +examples: >>>>> + - | >>>>> + rtc@20124000 { >>>>> + compatible = "microchip,mpfs-rtc"; >>>>> + reg = <0x20124000 0x1000>; >>>>> + clocks = <&clkcfg 21>; >>>>> + clock-names = "rtc"; >>>>> + interrupts = <80>, <81>; >>>>> + }; >>>>> +... >>>> >>> >>> -- >>> Alexandre Belloni, co-owner and COO, Bootlin >>> Embedded Linux and Kernel engineering >>> https://bootlin.com >> >
From: Conor Dooley <conor.dooley@microchip.com> This series updates the Microchip Icicle Kit device tree by adding a host of peripherals, and some updates to the memory map. In addition, the device tree has been split into a third part, which contains "soft" peripherals that are in the fpga fabric. Several of the entries are for peripherals that have not get had their drivers upstreamed, so in those cases the dt bindings are included where appropriate in order to avoid the many "DT compatible string <x> appears un-documented" errors. Depends on mpfs clock driver binding (on clk/next) to provide dt-bindings/clock/microchip,mpfs-clock.h for the device tree and on the other changes to the icicle/mpfs device tree from geert that are already in linux/riscv/for-next. Additionally, the interrupt-extended warnings on the plic/clint are cleared by [1] & [2]. [1] https://lore.kernel.org/linux-riscv/cover.1639744468.git.geert@linux-m68k.org/ [2] https://lore.kernel.org/linux-riscv/cover.1639744106.git.geert@linux-m68k.org/ Changes from v6: - Dropped i2c patch, as its in i2c-next - Added ack on gpio, reviewed-by on rtc - Dropped child nodes from sysctrl binding entirely, added a link to the online documenation for the services the system controller can provide - Dropped the #pwm-cells and replaced with a ref, a la Krzysztof's series Changes from v5: - reworded the descriptions in the pwm binding to (hopefully) add clarity - added -mask to the custom properties and made them 32 bit - renamed the i2c binding to corei2c, since it is not mpfs specific - removed the child nodes of the system controller in example/dts & will create them in the driver. @Rob, I assume keeping them documented is the correct thing to do? - removed the dependancy on the clock binding from the examples - reformatted rtc interrupts as per Rob's suggestion Changes from v4: - dont include icicle_kit_defconfig, accidentally added in v3 - drop prescaler from mpfs-rtc & calculate the value instead - use corei2c as a fallback device for mpfs-i2c - drop spi dt-binding (on spi-next) commit 2da187304e556ac59cf2dacb323cc78ded988169 - drop usb dt-binding (on usb-next) Changes from v3: - drop "mailbox: change mailbox-mpfs compatible string", already upstream: commit f10b1fc0161cd99e ("mailbox: change mailbox-mpfs compatible string") - fix copy paste error in microchip,mpfs-mailbox dt-binding - remove whitespace in syscontroller dt entry Changes from v2: - dropped plic int header & corresponding defines in dts{,i} - use $ref to drmode in mpfs-musb binding - split changes to dts{,i} again: functional changes to existing elements now are in a new patch - drop num-cs property in mpfs-spi binding - dont make the system controller a simple-mfd - move the separate bindings for rng/generic system services into the system controller binding - added an instance corei2c as i2c2 in the fabric dtsi - add version numbering to corepwm and corei2c compat string (-rtl-vN) Conor Dooley (11): dt-bindings: soc/microchip: update syscontroller compatibles dt-bindings: soc/microchip: add info about services to mpfs sysctrl dt-bindings: rtc: add bindings for microchip mpfs rtc dt-bindings: gpio: add bindings for microchip mpfs gpio dt-bindings: pwm: add microchip corepwm binding riscv: dts: microchip: use clk defines for icicle kit riscv: dts: microchip: add fpga fabric section to icicle kit riscv: dts: microchip: refactor icicle kit device tree riscv: dts: microchip: update peripherals in icicle kit device tree riscv: dts: microchip: add new peripherals to icicle kit device tree MAINTAINERS: update riscv/microchip entry .../bindings/gpio/microchip,mpfs-gpio.yaml | 79 ++++++ ...ilbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +- .../bindings/pwm/microchip,corepwm.yaml | 81 ++++++ .../bindings/rtc/microchip,mfps-rtc.yaml | 58 ++++ .../microchip,mpfs-sys-controller.yaml | 40 +++ ...icrochip,polarfire-soc-sys-controller.yaml | 35 --- MAINTAINERS | 2 + .../dts/microchip/microchip-mpfs-fabric.dtsi | 25 ++ .../microchip/microchip-mpfs-icicle-kit.dts | 115 ++++++-- .../boot/dts/microchip/microchip-mpfs.dtsi | 254 ++++++++++++++---- 10 files changed, 591 insertions(+), 104 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%) create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml delete mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi