| Message ID | 20230929-pxa1908-lkml-v5-0-5aa5a1109c5f@skole.hr |
|---|---|
| Headers | show |
| Series | Initial Marvell PXA1908 support | expand |
On Fri, Sep 29, 2023 at 5:42 PM Duje Mihanović <duje.mihanovic@skole.hr> wrote: > Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value > Edition LTE, a smartphone based on said SoC. > > Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> (...) > +&pmx { > + pinctrl-single,gpio-range = <&range 55 55 0>, > + <&range 110 32 0>, > + <&range 52 1 0>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&board_pins_1 &board_pins_2 &board_pins_3>; > + > + board_pins_1: pinmux-board-1 { > + pinctrl-single,pins = < > + 0x160 0 > + 0x164 0 > + 0x168 0 > + 0x16c 0 > + >; > + pinctrl-single,drive-strength = <0x1000 0x1800>; > + pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>; > + pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>; > + pinctrl-single,input-schmitt = <0 0x30>; > + pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>; > + pinctrl-single,low-power-mode = <0x288 0x388>; > + }; (...) > + pmx: pinmux@1e000 { > + compatible = "pinconf-single"; At least add a new binding for "marvell,pxa1908-padconf" and use that like this: compatible = "marvell,pxa1908-padconf", "pinconf-single"; When you use pinctrl-single you get the slightly opaque device trees as seen above, so it's not something I'd recommend, I'd rather write my own pin controller. But it exists, so I can't say you can't use it. Not my choice. I understand it is convenient. It is possible to switch later, but only if you have a unique pin controller compatible so please add that. Yours, Linus Walleij
On Fri, Sep 29, 2023 at 05:41:59PM +0200, Duje Mihanović wrote: > Add dt bindings and documentation for the Marvell PXA1908 clock > controller. > > Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > --- > .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ > include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++++++ > 2 files changed, 136 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml > new file mode 100644 > index 000000000000..4e78933232b6 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Marvell PXA1908 Clock Controllers > + > +maintainers: > + - Duje Mihanović <duje.mihanovic@skole.hr> > + > +description: | > + The PXA1908 clock subsystem generates and supplies clock to various > + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock > + controller blocks, with the ones currently supported being APBC, APBCP, MPMU > + and APMU roughly corresponding to internal buses. > + > + All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>. > + > +properties: > + compatible: > + enum: > + - marvell,pxa1908-apbc > + - marvell,pxa1908-apbcp > + - marvell,pxa1908-mpmu > + - marvell,pxa1908-apmu > + > + reg: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + # APMU block: > + - | > + clock-controller@d4282800 { > + compatible = "marvell,pxa1908-apmu"; > + reg = <0xd4282800 0x400>; > + #clock-cells = <1>; > + }; > diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h > new file mode 100644 > index 000000000000..fb15b0d0cd4c > --- /dev/null > +++ b/include/dt-bindings/clock/marvell,pxa1908.h > @@ -0,0 +1,88 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ > +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H > +#define __DTS_MARVELL_PXA1908_CLOCK_H > + > +/* plls */ > +#define PXA1908_CLK_CLK32 1 > +#define PXA1908_CLK_VCTCXO 2 > +#define PXA1908_CLK_PLL1_624 3 > +#define PXA1908_CLK_PLL1_416 4 > +#define PXA1908_CLK_PLL1_499 5 > +#define PXA1908_CLK_PLL1_832 6 > +#define PXA1908_CLK_PLL1_1248 7 > +#define PXA1908_CLK_PLL1_D2 8 > +#define PXA1908_CLK_PLL1_D4 9 > +#define PXA1908_CLK_PLL1_D8 10 > +#define PXA1908_CLK_PLL1_D16 11 > +#define PXA1908_CLK_PLL1_D6 12 > +#define PXA1908_CLK_PLL1_D12 13 > +#define PXA1908_CLK_PLL1_D24 14 > +#define PXA1908_CLK_PLL1_D48 15 > +#define PXA1908_CLK_PLL1_D96 16 > +#define PXA1908_CLK_PLL1_D13 17 > +#define PXA1908_CLK_PLL1_32 18 > +#define PXA1908_CLK_PLL1_208 19 > +#define PXA1908_CLK_PLL1_117 20 > +#define PXA1908_CLK_PLL1_416_GATE 21 > +#define PXA1908_CLK_PLL1_624_GATE 22 > +#define PXA1908_CLK_PLL1_832_GATE 23 > +#define PXA1908_CLK_PLL1_1248_GATE 24 > +#define PXA1908_CLK_PLL1_D2_GATE 25 > +#define PXA1908_CLK_PLL1_499_EN 26 > +#define PXA1908_CLK_PLL2VCO 27 > +#define PXA1908_CLK_PLL2 28 > +#define PXA1908_CLK_PLL2P 29 > +#define PXA1908_CLK_PLL2VCODIV3 30 > +#define PXA1908_CLK_PLL3VCO 31 > +#define PXA1908_CLK_PLL3 32 > +#define PXA1908_CLK_PLL3P 33 > +#define PXA1908_CLK_PLL3VCODIV3 34 > +#define PXA1908_CLK_PLL4VCO 35 > +#define PXA1908_CLK_PLL4 36 > +#define PXA1908_CLK_PLL4P 37 > +#define PXA1908_CLK_PLL4VCODIV3 38 > + > +/* apb (apbc) peripherals */ > +#define PXA1908_CLK_UART0 1 > +#define PXA1908_CLK_UART1 2 > +#define PXA1908_CLK_GPIO 3 > +#define PXA1908_CLK_PWM0 4 > +#define PXA1908_CLK_PWM1 5 > +#define PXA1908_CLK_PWM2 6 > +#define PXA1908_CLK_PWM3 7 > +#define PXA1908_CLK_SSP0 8 > +#define PXA1908_CLK_SSP1 9 > +#define PXA1908_CLK_IPC_RST 10 > +#define PXA1908_CLK_RTC 11 > +#define PXA1908_CLK_TWSI0 12 > +#define PXA1908_CLK_KPC 13 > +#define PXA1908_CLK_SWJTAG 14 > +#define PXA1908_CLK_SSP2 15 > +#define PXA1908_CLK_TWSI1 16 > +#define PXA1908_CLK_THERMAL 17 > +#define PXA1908_CLK_TWSI3 18 > + > +/* apb (apbcp) peripherals */ > +#define PXA1908_CLK_UART2 1 > +#define PXA1908_CLK_TWSI2 2 > +#define PXA1908_CLK_AICER 3 > + > +/* axi (apmu) peripherals */ > +#define PXA1908_CLK_CCIC1 1 > +#define PXA1908_CLK_ISP 2 > +#define PXA1908_CLK_DSI1 3 > +#define PXA1908_CLK_DISP1 4 > +#define PXA1908_CLK_CCIC0 5 > +#define PXA1908_CLK_SDH0 6 > +#define PXA1908_CLK_SDH1 7 > +#define PXA1908_CLK_USB 8 > +#define PXA1908_CLK_NF 9 > +#define PXA1908_CLK_CORE_DEBUG 10 > +#define PXA1908_CLK_VPU 11 > +#define PXA1908_CLK_GC 12 > +#define PXA1908_CLK_SDH2 13 > +#define PXA1908_CLK_GC2D 14 > +#define PXA1908_CLK_TRACE 15 > +#define PXA1908_CLK_DVC_DFC_DEBUG 16 > + > +#endif > > -- > 2.42.0 > >
On Sat, Sep 30, 2023 at 10:25 AM Duje Mihanović <duje.mihanovic@skole.hr> wrote: > On Saturday, September 30, 2023 12:05:41 AM CEST Linus Walleij wrote: > > But it exists, so I can't say you can't use it. Not my choice. > > I understand it is convenient. > > > > It is possible to switch later, but only if you have a unique > > pin controller compatible so please add that. > > Maybe a dumb question. I might want to do this at some point to clean up the > device tree a bit, are there any such pinctrl drivers I can use as a > reference? Since it's Marvell after all (albeit a descendant of the 20 yo PXA platform!) I would expect new Marvell SoCs to be more alike the AC5 bindings that Chris Packham merged only last year: Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml Driver: drivers/pinctrl/mvebu/pinctrl-armada-xp.c drivers/pinctrl/mvebu/pinctrl-mvebu.c But if this pin controller is more related to PXA (Intel) hardware than to either Kirkwood or Armada, you might want to do something entirely different. It depends a bit on hardware. Hardware such as pinctrl-single.c with one mux configuration register per pin usually follow the Qualcomm way of doing things, which is to simply have one group per pin, then that can be associated with desired functions: Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml this has the upside of using all the standard bindings for bias etc. Driver: drivers/pinctrl/qcom/pinctrl-msm.c then qualcomm have subdrivers for each SoC calling into this so you have to check "real" bindings and drivers such as: Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml drivers/pinctrl/qcom/pinctrl-sm8550.c Yours, Linus Walleij
On Fri, Sep 29, 2023 at 5:42 PM Duje Mihanović <duje.mihanovic@skole.hr> wrote: > > Similarly to PXA3xx and MMP2, pinctrl-single isn't capable of setting > pin direction on MMP either. > > Fixes: a770d946371e ("gpio: pxa: add pin control gpio direction and request") > Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> > Reviewed-by: Andy Shevchenko <andy@kernel.org> > --- > drivers/gpio/gpio-pxa.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c > index a1630ed4b741..d92650aecb06 100644 > --- a/drivers/gpio/gpio-pxa.c > +++ b/drivers/gpio/gpio-pxa.c > @@ -238,6 +238,7 @@ static bool pxa_gpio_has_pinctrl(void) > switch (gpio_type) { > case PXA3XX_GPIO: > case MMP2_GPIO: > + case MMP_GPIO: > return false; > > default: > > -- > 2.42.0 > > Queued for fixes, thanks! Bart
Hello, This series adds initial support for the Marvell PXA1908 SoC and "samsung,coreprimevelte", a smartphone using the SoC. USB works and the phone can boot a rootfs from an SD card, but there are some warnings in the dmesg: During SMP initialization: [ 0.006519] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000 [ 0.006542] CPU features: Unsupported CPU feature variation detected. [ 0.006589] CPU1: Booted secondary processor 0x0000000001 [0x410fd032] [ 0.010710] Detected VIPT I-cache on CPU2 [ 0.010716] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000 [ 0.010758] CPU2: Booted secondary processor 0x0000000002 [0x410fd032] [ 0.014849] Detected VIPT I-cache on CPU3 [ 0.014855] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000 [ 0.014895] CPU3: Booted secondary processor 0x0000000003 [0x410fd032] SMMU probing fails: [ 0.101798] arm-smmu c0010000.iommu: probing hardware configuration... [ 0.101809] arm-smmu c0010000.iommu: SMMUv1 with: [ 0.101816] arm-smmu c0010000.iommu: no translation support! On Samsung's PXA1908 phones, the bootloader does not start the ARM system timer, and my temporary solution (which isn't present in this series) was to put the code for starting the timer in the clock driver. Would this hack be accepted upstream in the form of a platform or clocksource driver such as drivers/clocksource/timer-mediatek-cpux.c? A 3.14 based Marvell tree is available on GitHub acorn-marvell/brillo_pxa_kernel, and a Samsung one on GitHub CoderCharmander/g361f-kernel. Andreas Färber attempted to upstream support for this SoC in 2017: https://lore.kernel.org/lkml/20170222022929.10540-1-afaerber@suse.de/ Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> --- Changes in v5: - Address maintainer comments: - Move *_NR_CLKS to clock driver from dt binding file - Allocate correct number of clocks for each block instead of blindly allocating 50 for each - Link to v4: https://lore.kernel.org/r/20230807-pxa1908-lkml-v4-0-cb387d73b452@skole.hr Changes in v4: - Address maintainer comments: - Relicense clock binding file to BSD-2 - Add pinctrl-names to SD card node - Add vgic registers to GIC node - Rebase on v6.5-rc5 - Link to v3: https://lore.kernel.org/r/20230804-pxa1908-lkml-v3-0-8e48fca37099@skole.hr Changes in v3: - Address maintainer comments: - Drop GPIO dynamic allocation patch - Move clock register offsets into driver (instead of bindings file) - Add missing Tested-by trailer to u32_fract patch - Move SoC binding to arm/mrvl/mrvl.yaml - Add serial0 alias and stdout-path to board dts to enable UART debugging - Rebase on v6.5-rc4 - Link to v2: https://lore.kernel.org/r/20230727162909.6031-1-duje.mihanovic@skole.hr Changes in v2: - Remove earlycon patch as it's been merged into tty-next - Address maintainer comments: - Clarify GPIO regressions on older PXA platforms - Add Fixes tag to commit disabling GPIO pinctrl calls for this SoC - Add missing includes to clock driver - Clock driver uses HZ_PER_MHZ, u32_fract and GENMASK - Dual license clock bindings - Change clock IDs to decimal - Fix underscores in dt node names - Move chosen node to top of board dts - Clean up documentation - Reorder commits - Drop pxa,rev-id - Rename muic-i2c to i2c-muic - Reword some commits - Move framebuffer node to chosen - Add aliases for mmc nodes - Rebase on v6.5-rc3 - Link to v1: https://lore.kernel.org/r/20230721210042.21535-1-duje.mihanovic@skole.hr --- Andy Shevchenko (1): clk: mmp: Switch to use struct u32_fract instead of custom one Duje Mihanović (7): gpio: pxa: disable pinctrl calls for MMP_GPIO dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Add Marvell PXA1908 clock driver dt-bindings: marvell: Document PXA1908 SoC arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte MAINTAINERS: add myself as Marvell PXA1908 maintainer .../devicetree/bindings/arm/mrvl/mrvl.yaml | 5 + .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 +++ MAINTAINERS | 9 + arch/arm64/Kconfig.platforms | 11 + arch/arm64/boot/dts/marvell/Makefile | 3 + .../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 333 +++++++++++++++++++++ arch/arm64/boot/dts/marvell/pxa1908.dtsi | 295 ++++++++++++++++++ drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-frac.c | 57 ++-- drivers/clk/mmp/clk-mmp2.c | 6 +- drivers/clk/mmp/clk-of-mmp2.c | 26 +- drivers/clk/mmp/clk-of-pxa168.c | 4 +- drivers/clk/mmp/clk-of-pxa1908.c | 328 ++++++++++++++++++++ drivers/clk/mmp/clk-of-pxa1928.c | 6 +- drivers/clk/mmp/clk-of-pxa910.c | 4 +- drivers/clk/mmp/clk-pxa168.c | 4 +- drivers/clk/mmp/clk-pxa910.c | 4 +- drivers/clk/mmp/clk.h | 10 +- drivers/gpio/gpio-pxa.c | 1 + include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++ 20 files changed, 1180 insertions(+), 64 deletions(-) --- base-commit: 52a93d39b17dc7eb98b6aa3edb93943248e03b2f change-id: 20230803-pxa1908-lkml-6830e8da45c7 Best regards,