mbox series

[0/3] pinctrl: imx-scmi: Introdue nxp,iomuxc-daisy-off

Message ID 20250512-pin-v1-0-d9f1555a55ad@nxp.com
Headers show
Series pinctrl: imx-scmi: Introdue nxp,iomuxc-daisy-off | expand

Message

Peng Fan May 12, 2025, 2:14 a.m. UTC 
It might be a bit late, since it is 6.15-RC6 now. No rush, the target is 6.17.

i.MX9 SoC family IOMUXC features Daisy chain(multi pads driving same module
input pin), each SoC has its own daisy register offset. When add a new SoC
support, need to hardcode the register offset in pinctrl-imx-scmi.c just as
"
if (of_machine_is_compatible("fsl,imx95"))
   daisy_off = IMX95_DAISY_OFF;
else if
   ...
else
   ...
"

This is no good to long term maintainence.

With nxp,iomuxc-daisy-off introduced, things will be simplified to set
daisy register offset:
"device_property_read_u32(dev, "nxp,iomuxc-daisy-off", &pmx->daisy_off);"

The new property is set as required, so there might be dtbs_check error
without patch 3 applied. This is expected.

Patchset based on next-20250508

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Peng Fan (3):
      dt-bindings: firmware: nxp,imx95-scmi-pinctrl: Introduce nxp,iomuxc-daisy-off
      pinctrl: imx-scmi: Get daisy register offset from DT
      arm64: dts: imx95: Add property nxp,iomuxc-daisy-off

 .../bindings/firmware/nxp,imx95-scmi-pinctrl.yaml  |  8 +++++++
 arch/arm64/boot/dts/freescale/imx95.dtsi           |  1 +
 drivers/pinctrl/freescale/pinctrl-imx-scmi.c       | 26 +++++++++++++---------
 3 files changed, 24 insertions(+), 11 deletions(-)
---
base-commit: f48887a98b78880b7711aca311fbbbcaad6c4e3b
change-id: 20250509-pin-e5b563bbd55d

Best regards,