From patchwork Wed Jun 30 14:50:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 468898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10539C11F69 for ; Wed, 30 Jun 2021 14:50:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA58661483 for ; Wed, 30 Jun 2021 14:50:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235715AbhF3OxS (ORCPT ); Wed, 30 Jun 2021 10:53:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235621AbhF3OxS (ORCPT ); Wed, 30 Jun 2021 10:53:18 -0400 Received: from xavier.telenet-ops.be (xavier.telenet-ops.be [IPv6:2a02:1800:120:4::f00:14]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE3D3C061767 for ; Wed, 30 Jun 2021 07:50:48 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:7d95:f75f:5ece:4663]) by xavier.telenet-ops.be with bizsmtp id PSql250034F6zkK01SqlE1; Wed, 30 Jun 2021 16:50:45 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1lybY4-0059dJ-Rw; Wed, 30 Jun 2021 16:50:44 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1lybY4-005c5x-9t; Wed, 30 Jun 2021 16:50:44 +0200 From: Geert Uytterhoeven To: Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 0/2] pinctrl: renesas: Add r8a77995 bias pinconf support Date: Wed, 30 Jun 2021 16:50:41 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi all, This patch series adds a small optimization to R-Car pin bias handling, and adds bias pinconf support for the R-Car D3 SoC. Changes compared to v1[1]: - Drop all accepted patches, - Add [PATCH v2 1/2], - Add Reviewed-by, - Fix NFRE# and NFWE# handling, now we received confirmation that the documentation is correct. The first patch has been tested on Koelsch and Salvator-XS. The second patch has been tested on a remote Draak development board by specifying one of the "bias-{pull-{down,enable},disable}" properties for the "GP_3_0" and "GP_3_1" pins from DT, and inspecting the impact on the PUEN2 and PUD2 registers. Due to the remote setup, actual voltage levels could not be measured. Note that enabling pull-down for "GP_3_0" breaks eMMC operation, as this pin is used as the eMMC's "CMD" signal. I plan to queue this in renesas-pinctrl for v5.15. Thanks for your comments! [1] [PATCH 00/12] pinctrl: renesas: Add more bias pinconf support https://lore.kernel.org/linux-renesas-soc/cover.1619785375.git.geert+renesas@glider.be/ Geert Uytterhoeven (2): pinctrl: renesas: rcar: Avoid changing PUDn when disabling bias pinctrl: renesas: r8a77995: Add bias pinconf support drivers/pinctrl/renesas/pfc-r8a77995.c | 320 ++++++++++++++++++++++++- drivers/pinctrl/renesas/pinctrl.c | 16 +- drivers/pinctrl/renesas/sh_pfc.h | 3 + 3 files changed, 323 insertions(+), 16 deletions(-) Reviewed-by: Niklas Söderlund