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[209.132.180.67]) by mx.google.com with ESMTP id s26si12711651pfi.57.2015.12.09.05.15.20; Wed, 09 Dec 2015 05:15:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro-org.20150623.gappssmtp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754080AbbLINPT (ORCPT + 4 others); Wed, 9 Dec 2015 08:15:19 -0500 Received: from mail-lf0-f42.google.com ([209.85.215.42]:33588 "EHLO mail-lf0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751617AbbLINPS (ORCPT ); Wed, 9 Dec 2015 08:15:18 -0500 Received: by lfaz4 with SMTP id z4so33961747lfa.0 for ; Wed, 09 Dec 2015 05:15:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=LkK/Ya4HKvdG/WW3WRTdGD1mZXRd7EEPwnz5qKJKV9g=; b=qSDPAGqUxiEN/RB1zDBSJ0Fhl5OFXxxLVR/sT4T20lDl1E6ZiDqP/U4lwb8vxpTt8m BZzoeqCdERQ/0eJ3MBKPLeSYqPRPMXuW9qaeEIhUHq2mRuhH8VbGSbITQWEES5nPHWqw D5Z19lobWaM/yCy624r05jqr/sYrABCGAhRHPiKGucU1qKD+eHUluTBb39N0JQjlMvd3 boS5/v9hMqo5SmwotC0m9lcVZl2ubJzy1KtTj5I4argHfETfC+5ub4B4PWvqFtEwVTS3 mAFQe3xtbNkE6n1KrETN+QZ40+1Kr9kKWRDgR1n9eKnAnPYnAuDsS+wOE59NPDsqWPJV iAGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=LkK/Ya4HKvdG/WW3WRTdGD1mZXRd7EEPwnz5qKJKV9g=; b=QkOhOm7tXiuxUNQO+vDtA+1BTdOHkOzCPrthuoEs/JhsJt0ZY6MgdZGOiMBBi7FvsC pq3hIMhx5usNyNNSv2zaTDAFBpner4OA0Ev+XAK6v866ygZ5Ebgj/2536g5tDTPKvKEE ysuxcGA5NJcOlTGPYkdHJu/3LuyhufiA461Zu6F6jDxrV5pLRM3R9uEbX4P0ksHUKIBj LfawMxkGrOmOR2VofEd3A8M9EQKPHvnWNAqxD2DLDRUUcVj3dW/hbr8vTYSLdhEQ0x6S 4LFBj1BXUPsTkwAZZdabXLUYgOV0Puantj2Qz/g6xGB9cBx7C/H2UE7hFKKj20WUUSbL FvOA== X-Gm-Message-State: ALoCoQlxh6/h61waA8jVSiVmVG2u87NERgTnResUH9pHwxwv2VZ6kePJTKycu+Tb8CigXdRMWxDRVnwQT5uYnzcbsD8M7EQVYg== X-Received: by 10.25.207.14 with SMTP id f14mr1833789lfg.29.1449666916839; Wed, 09 Dec 2015 05:15:16 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id g7sm1395311lbs.34.2015.12.09.05.15.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Dec 2015 05:15:16 -0800 (PST) From: Linus Walleij To: linux-gpio@vger.kernel.org, Johan Hovold , Alexandre Courbot , Michael Welling , Markus Pargmann Cc: Linus Walleij , Shobhit Kumar , "Zhu, Lejun" Subject: [PATCH 018/182] gpio: crystalcove: use gpiochip data pointer Date: Wed, 9 Dec 2015 14:15:11 +0100 Message-Id: <1449666911-30596-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This makes the driver use the data pointer added to the gpio_chip to store a pointer to the state container instead of relying on container_of(). Cc: Shobhit Kumar Cc: Zhu, Lejun Signed-off-by: Linus Walleij --- drivers/gpio/gpio-crystalcove.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c index 141093a8cd3f..7865ef0d3352 100644 --- a/drivers/gpio/gpio-crystalcove.c +++ b/drivers/gpio/gpio-crystalcove.c @@ -86,11 +86,6 @@ struct crystalcove_gpio { bool set_irq_mask; }; -static inline struct crystalcove_gpio *to_cg(struct gpio_chip *gc) -{ - return container_of(gc, struct crystalcove_gpio, chip); -} - static inline int to_reg(int gpio, enum ctrl_register reg_type) { int reg; @@ -134,7 +129,7 @@ static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio) static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) { - struct crystalcove_gpio *cg = to_cg(chip); + struct crystalcove_gpio *cg = gpiochip_get_data(chip); if (gpio > CRYSTALCOVE_VGPIO_NUM) return 0; @@ -146,7 +141,7 @@ static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio) static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int value) { - struct crystalcove_gpio *cg = to_cg(chip); + struct crystalcove_gpio *cg = gpiochip_get_data(chip); if (gpio > CRYSTALCOVE_VGPIO_NUM) return 0; @@ -157,7 +152,7 @@ static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio) { - struct crystalcove_gpio *cg = to_cg(chip); + struct crystalcove_gpio *cg = gpiochip_get_data(chip); int ret; unsigned int val; @@ -174,7 +169,7 @@ static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio) static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) { - struct crystalcove_gpio *cg = to_cg(chip); + struct crystalcove_gpio *cg = gpiochip_get_data(chip); if (gpio > CRYSTALCOVE_VGPIO_NUM) return; @@ -187,7 +182,8 @@ static void crystalcove_gpio_set(struct gpio_chip *chip, static int crystalcove_irq_type(struct irq_data *data, unsigned type) { - struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); + struct crystalcove_gpio *cg = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); switch (type) { case IRQ_TYPE_NONE: @@ -213,14 +209,16 @@ static int crystalcove_irq_type(struct irq_data *data, unsigned type) static void crystalcove_bus_lock(struct irq_data *data) { - struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); + struct crystalcove_gpio *cg = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); mutex_lock(&cg->buslock); } static void crystalcove_bus_sync_unlock(struct irq_data *data) { - struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); + struct crystalcove_gpio *cg = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); int gpio = data->hwirq; if (cg->update & UPDATE_IRQ_TYPE) @@ -234,7 +232,8 @@ static void crystalcove_bus_sync_unlock(struct irq_data *data) static void crystalcove_irq_unmask(struct irq_data *data) { - struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); + struct crystalcove_gpio *cg = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); cg->set_irq_mask = false; cg->update |= UPDATE_IRQ_MASK; @@ -242,7 +241,8 @@ static void crystalcove_irq_unmask(struct irq_data *data) static void crystalcove_irq_mask(struct irq_data *data) { - struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data)); + struct crystalcove_gpio *cg = + gpiochip_get_data(irq_data_get_irq_chip_data(data)); cg->set_irq_mask = true; cg->update |= UPDATE_IRQ_MASK; @@ -288,7 +288,7 @@ static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data) static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { - struct crystalcove_gpio *cg = to_cg(chip); + struct crystalcove_gpio *cg = gpiochip_get_data(chip); int gpio, offset; unsigned int ctlo, ctli, mirqs0, mirqsx, irq; @@ -345,7 +345,7 @@ static int crystalcove_gpio_probe(struct platform_device *pdev) cg->chip.dbg_show = crystalcove_gpio_dbg_show; cg->regmap = pmic->regmap; - retval = gpiochip_add(&cg->chip); + retval = gpiochip_add_data(&cg->chip, cg); if (retval) { dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval); return retval;