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[209.132.180.67]) by mx.google.com with ESMTP id o14si1374673pli.164.2017.09.20.06.40.33; Wed, 20 Sep 2017 06:40:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=KX1uLyqK; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751837AbdITNkb (ORCPT + 5 others); Wed, 20 Sep 2017 09:40:31 -0400 Received: from mail-wr0-f171.google.com ([209.85.128.171]:56565 "EHLO mail-wr0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751743AbdITNjo (ORCPT ); Wed, 20 Sep 2017 09:39:44 -0400 Received: by mail-wr0-f171.google.com with SMTP id r74so2183940wrb.13 for ; Wed, 20 Sep 2017 06:39:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Q6SPt7E8EFFA37vG/DeJoLrRPd9ktmwC85Tt2b0FGio=; b=KX1uLyqK5z1299W5cpLRnEtRtObkXi46YACkkJmZckGYTMuaPQJktiaGNTiX4VEJiw AzNsMW97QYkeNgqdkUXIa0YkOwCsMVDdd9RPVn848mLpfPyL263NqZ4ifbglpxMhjJuH 0hC1wb+3UQDNPcLV5RmYKhdarj/V2R18A7WRo6uZtsqfv7Z6zJTTqIkzIdzBTBynnNUs kY7OGJGEkWm9i4I4k/4OgL5445Nb/LvBqPekkeJFRaIMGMEnr7tONQBR2C+/wln3S0PW EoE8QbMJZF0IbqP5uYzFDOcUWAWpfMZccsy+Z0xlCJYAOMmxP97wX8VOBmW4+hFqvSAf lHNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q6SPt7E8EFFA37vG/DeJoLrRPd9ktmwC85Tt2b0FGio=; b=eiJ6YVxDZqlJDsaQcKQKnrt/l4tf3I+mxpaInSU/dcg3upjr+y1fcdnaTMvIGKNRBG ARhAj6IGaC33bQfvQYirg+rExbSz1dKLgrzka6htjLzV1EFQCAr57+ya+9Mcvv0WNxjr R1J06xhfYJHf4VdL6tWVki5Nhop4OT236ZuTcUIMOYiGA/7T7t8360Kt5iIRkfQPYHnD qcojsCWuiig8vmnUsFlCWSBedOeaT+9mgyP7r+ZycPGoIrdSEmS2L+ho9CD9NUVi1S9Q xElcWhe8JQUxQfNLtOQHkX/Y+DLYCWY26SccTcrxjw5R4YpGUsJMLm0XiUOCYiajsfF2 Nimg== X-Gm-Message-State: AHPjjUilR5pKO/vgY4U7Shpx6L4drq9pDZ60dKJY/Q+sa8WPxcRopnJu qWpg0cacU46+MK25nC0RiwdIeQ== X-Google-Smtp-Source: AOwi7QBPazFvKRdeiaClkL1mGUXbq0fJAo9um9S9eabqMcIH/o8YGXPMG63SvQ3h53+GDppznZS5fw== X-Received: by 10.223.150.27 with SMTP id b27mr4616963wra.100.1505914783169; Wed, 20 Sep 2017 06:39:43 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id a39sm1938888wrc.48.2017.09.20.06.39.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 06:39:42 -0700 (PDT) From: Jerome Brunet To: Linus Walleij , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Martin Blumenstingl Subject: [PATCH 6/8] pinctrl: meson: get rid of pin_base Date: Wed, 20 Sep 2017 15:39:25 +0200 Message-Id: <20170920133927.17390-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170920133927.17390-1-jbrunet@baylibre.com> References: <20170920133927.17390-1-jbrunet@baylibre.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org pin_base was used with the manually set pin offset in meson pinctrl. This is no longer the case, pin_base is 0 on every meson pinctrl controllers and should go away. Tested-by: Martin Blumenstingl Signed-off-by: Jerome Brunet --- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 2 -- drivers/pinctrl/meson/pinctrl-meson-gxl.c | 2 -- drivers/pinctrl/meson/pinctrl-meson.c | 30 +++++++++++++----------------- drivers/pinctrl/meson/pinctrl-meson8.c | 2 -- drivers/pinctrl/meson/pinctrl-meson8b.c | 2 -- 5 files changed, 13 insertions(+), 25 deletions(-) -- 2.13.5 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 6d52842d3ee5..8e0d6e4a31b4 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -820,7 +820,6 @@ static struct meson_bank meson_gxbb_aobus_banks[] = { struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { .name = "periphs-banks", - .pin_base = 0, .pins = meson_gxbb_periphs_pins, .groups = meson_gxbb_periphs_groups, .funcs = meson_gxbb_periphs_functions, @@ -833,7 +832,6 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { .name = "aobus-banks", - .pin_base = 0, .pins = meson_gxbb_aobus_pins, .groups = meson_gxbb_aobus_groups, .funcs = meson_gxbb_aobus_functions, diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 32e35ba9c04e..0d90ddab6ddd 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -807,7 +807,6 @@ static struct meson_bank meson_gxl_aobus_banks[] = { struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { .name = "periphs-banks", - .pin_base = 0, .pins = meson_gxl_periphs_pins, .groups = meson_gxl_periphs_groups, .funcs = meson_gxl_periphs_functions, @@ -820,7 +819,6 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { .name = "aobus-banks", - .pin_base = 0, .pins = meson_gxl_aobus_pins, .groups = meson_gxl_aobus_groups, .funcs = meson_gxl_aobus_functions, diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 247208150b19..c9cd54de0449 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -413,16 +413,15 @@ static const struct pinconf_ops meson_pinconf_ops = { static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, pin; + unsigned int reg, bit; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); } @@ -431,21 +430,20 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, pin; + unsigned int reg, bit; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_DIR, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_DIR, ®, &bit); ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), value ? BIT(bit) : 0); } @@ -453,16 +451,15 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, pin; + unsigned int reg, bit; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return; - meson_calc_reg_and_bit(bank, pin, REG_OUT, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_OUT, ®, &bit); regmap_update_bits(pc->reg_gpio, reg, BIT(bit), value ? BIT(bit) : 0); } @@ -470,16 +467,15 @@ static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) { struct meson_pinctrl *pc = gpiochip_get_data(chip); - unsigned int reg, bit, val, pin; + unsigned int reg, bit, val; struct meson_bank *bank; int ret; - pin = pc->data->pin_base + gpio; - ret = meson_get_bank(pc, pin, &bank); + ret = meson_get_bank(pc, gpio, &bank); if (ret) return ret; - meson_calc_reg_and_bit(bank, pin, REG_IN, ®, &bit); + meson_calc_reg_and_bit(bank, gpio, REG_IN, ®, &bit); regmap_read(pc->reg_gpio, reg, &val); return !!(val & BIT(bit)); diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index 7344f8577467..fbf8ecd1c2b6 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -1046,7 +1046,6 @@ static struct meson_bank meson8_aobus_banks[] = { struct meson_pinctrl_data meson8_cbus_pinctrl_data = { .name = "cbus-banks", - .pin_base = 0, .pins = meson8_cbus_pins, .groups = meson8_cbus_groups, .funcs = meson8_cbus_functions, @@ -1059,7 +1058,6 @@ struct meson_pinctrl_data meson8_cbus_pinctrl_data = { struct meson_pinctrl_data meson8_aobus_pinctrl_data = { .name = "ao-bank", - .pin_base = 0, .pins = meson8_aobus_pins, .groups = meson8_aobus_groups, .funcs = meson8_aobus_functions, diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index c3c247bfbc60..7af296db48c8 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -906,7 +906,6 @@ static struct meson_bank meson8b_aobus_banks[] = { struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { .name = "cbus-banks", - .pin_base = 0, .pins = meson8b_cbus_pins, .groups = meson8b_cbus_groups, .funcs = meson8b_cbus_functions, @@ -919,7 +918,6 @@ struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { .name = "aobus-banks", - .pin_base = 0, .pins = meson8b_aobus_pins, .groups = meson8b_aobus_groups, .funcs = meson8b_aobus_functions,