From patchwork Mon Nov 6 20:27:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 118098 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3175590qgn; Mon, 6 Nov 2017 12:29:42 -0800 (PST) X-Google-Smtp-Source: ABhQp+QSGfkTY/7wpWAEllA8sKaXYuhG1hSxofucF/hShgZi6heFML4rn+TPQu+Kc5Fb3NMM7m2H X-Received: by 10.98.159.210 with SMTP id v79mr17839794pfk.162.1510000182470; Mon, 06 Nov 2017 12:29:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510000182; cv=none; d=google.com; s=arc-20160816; b=N7anpvdBfe4fVWHlwIqEOuqu80D/IDz2JxKD5310mHHlq1RrGwKLKESj0/bUt4Fmqc 6pYv1MKg3+DEcsGunk9yKEWQNULQQI9UUCYqhgdV71KqC7qemIuMM/cHH+0KxV/JaYgG 4uchyZqTi1ULnn2MqqGCfYfKyaDu7tQFg+XPj8lHnmRXD+vkhtJBXz8lzPuj0cY3vD/C VWB6XD2cflHqusuOX/ZPMCH6zeXXcKj1Cf6gCno2NDOoooBLWo84Wyi/KxKS0lYXPbXo LpwDqDWJ7Bim1WWoAxTiSsQ/+lX1TjBSBS+nSbaU1LN68QzWD8Bqc28ioWRa/xhzWvfO ziyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=Rcrj6cD1eQvPwZcQ6yNYGwvZ1WHYUfBMTqZs6pGDgf0=; b=h2Cs2CILmJPgJQk3K/6awiW85jzohB9UsQNx/3qdcNrQ1BUGOOTibC0YtupwT2Juq8 udekwIwykzqqnMSfyZIDdkLigQwXhyB/Uh6pY0ooiVo4dOJ8sVTH4HED7CzD+tl1tCp4 ONbYsS5R9oZ2cl0POqMSHw/uzDmV/juUg7EihYFqsnE/LJBVQhCKKOYvOQVuoask+6c7 +Vo8X+k5t2HJSHlZJR5erRCCglpOy3ErY4WOyi0ODl/BoicRQoDQOVtkbLGWL51BWOQg JFk3Bhl2tnH5AHQ9Ky/w7R2LOYK5R3COyQPBHmCtaLNILUgyBlhZCqXXUaojbwyHVKpu JIzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OnQTlahJ; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e7si10577148plk.481.2017.11.06.12.29.42; Mon, 06 Nov 2017 12:29:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OnQTlahJ; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932837AbdKFU3l (ORCPT + 6 others); Mon, 6 Nov 2017 15:29:41 -0500 Received: from mail-lf0-f66.google.com ([209.85.215.66]:54705 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932655AbdKFU3k (ORCPT ); Mon, 6 Nov 2017 15:29:40 -0500 Received: by mail-lf0-f66.google.com with SMTP id a2so11921902lfh.11 for ; Mon, 06 Nov 2017 12:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=1tDCP6U9HdH02ppVRZsmBJumIYmjNCpzUXmOF7nWfs4=; b=OnQTlahJRxI2GxRXef70hrNV0iO/m0Ufv2yiqQjzisggzSR8aejhxXWmTPhagqzzb5 TE4JvNLtNfqd6Ft6VSjgzGyQAgfWuGILfaz2qaZaGpE15Cr8lLXYgArFuApE+5liTzbb uxkZRaYj+7d2ONVJOhN/TUdDSx3pm48ljlV8I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=1tDCP6U9HdH02ppVRZsmBJumIYmjNCpzUXmOF7nWfs4=; b=S3TB9KuiedicxzN7VRdGzMTxWAwSWLgQBP2HBqLFtDlakAlPKPcU4yZ2S5fbjj96Qu cpqx+Z2txi46CGhq7PQKAY6EJSl5EtgR4WLOE/OXXzPOwPDeum9ta2PjceAYBHXDib2Q e0OL8+YTGaU34Qq/pgDCP84pG7IG/juurzN9WcpihQ7ROh4L+pzHoe9BcBJpEu6Nzwvd gBL/YwZVZtNe40/TCrive03B7o11nefro/REfdDJZX6wm6VD7/OPxduYdYp7YrMIMggf gN9OZa7zw2MJBo3bTR75tDJ1UkBKUD2ZnJUOSb8jVhPFOYayjxlJZ8+LjA0GcsED1lC3 kv8Q== X-Gm-Message-State: AJaThX6qwqtFVKksuzE9+2Zv/oKpfe8gICV+609hgANLTPC96iLayvQ5 GNrKJpWCKYAV58DF53SQWJ7VtQ== X-Received: by 10.25.215.138 with SMTP id q10mr5896820lfi.208.1510000179037; Mon, 06 Nov 2017 12:29:39 -0800 (PST) Received: from localhost.localdomain (c-567171d5.014-348-6c756e10.cust.bredbandsbolaget.se. [213.113.113.86]) by smtp.gmail.com with ESMTPSA id h82sm2524830lfb.21.2017.11.06.12.29.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 06 Nov 2017 12:29:37 -0800 (PST) From: Linus Walleij To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH] pinctrl: gemini: Fix GMAC groups Date: Mon, 6 Nov 2017 21:27:34 +0100 Message-Id: <20171106202734.4891-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.13.6 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The GMII groups need to be split across GMAC0 and GMAC1 since GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7 so we might want just one interface out. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-gemini.c | 79 +++++++++++++++++++++++++++------------- 1 file changed, 54 insertions(+), 25 deletions(-) -- 2.13.6 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index bd6133f06759..ecfc9733db7e 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -96,6 +96,13 @@ struct gemini_pin_group { * you are stuck with it. */ #define GLOBAL_MISC_CTRL 0x30 +#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27) +/* Not really used */ +#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28) +/* Activated with GMAC1 */ +#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27) +/* This will be the default */ +#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0 #define TVC_CLK_PAD_ENABLE BIT(20) #define PCI_CLK_PAD_ENABLE BIT(17) #define LPC_CLK_PAD_ENABLE BIT(16) @@ -109,8 +116,8 @@ struct gemini_pin_group { #define NAND_PADS_DISABLE BIT(2) #define PFLASH_PADS_DISABLE BIT(1) #define SFLASH_PADS_DISABLE BIT(0) -#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20)) -#define PADS_MAXBIT 20 +#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27)) +#define PADS_MAXBIT 27 /* Ordered by bit index */ static const char * const gemini_padgroups[] = { @@ -516,9 +523,12 @@ static const unsigned int usb_3512_pins[] = { }; /* GMII, ethernet pins */ -static const unsigned int gmii_3512_pins[] = { - 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296, - 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281 +static const unsigned int gmii_gmac0_3512_pins[] = { + 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313 +}; + +static const unsigned int gmii_gmac1_3512_pins[] = { + 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317 }; static const unsigned int pci_3512_pins[] = { @@ -668,10 +678,10 @@ static const unsigned int gpio1c_3512_pins[] = { /* The GPIO1D (28-31) pins overlap with LCD and TVC */ static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; -/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ +/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; -/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ +/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; /* The GPIO2C (8-31) pins overlap with PCI */ @@ -738,9 +748,16 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { .num_pins = ARRAY_SIZE(usb_3512_pins), }, { - .name = "gmiigrp", - .pins = gmii_3512_pins, - .num_pins = ARRAY_SIZE(gmii_3512_pins), + .name = "gmii_gmac0_grp", + .pins = gmii_gmac0_3512_pins, + .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), + }, + { + .name = "gmii_gmac1_grp", + .pins = gmii_gmac1_3512_pins, + .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), + /* Bring out RGMII on the GMAC1 pins */ + .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "pcigrp", @@ -954,14 +971,15 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { .name = "gpio2agrp", .pins = gpio2a_3512_pins, .num_pins = ARRAY_SIZE(gpio2a_3512_pins), - /* Conflict with GMII and extended parallel flash */ + .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, + /* Conflict with GMII GMAC1 and extended parallel flash */ }, { .name = "gpio2bgrp", .pins = gpio2b_3512_pins, .num_pins = ARRAY_SIZE(gpio2b_3512_pins), - /* Conflict with GMII, extended parallel flash and LCD */ - .mask = LCD_PADS_ENABLE, + /* Conflict with GMII GMAC1, extended parallel flash and LCD */ + .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "gpio2cgrp", @@ -1441,9 +1459,12 @@ static const unsigned int usb_3516_pins[] = { }; /* GMII, ethernet pins */ -static const unsigned int gmii_3516_pins[] = { - 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347, - 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391 +static const unsigned int gmii_gmac0_3516_pins[] = { + 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387 +}; + +static const unsigned int gmii_gmac1_3516_pins[] = { + 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391 }; static const unsigned int pci_3516_pins[] = { @@ -1585,10 +1606,10 @@ static const unsigned int gpio1c_3516_pins[] = { /* The GPIO1D (28-31) pins overlap with TVC */ static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; -/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ +/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; -/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ +/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; /* The GPIO2C (8-31) pins overlap with PCI */ @@ -1660,9 +1681,16 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { .num_pins = ARRAY_SIZE(usb_3516_pins), }, { - .name = "gmiigrp", - .pins = gmii_3516_pins, - .num_pins = ARRAY_SIZE(gmii_3516_pins), + .name = "gmii_gmac0_grp", + .pins = gmii_gmac0_3516_pins, + .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), + }, + { + .name = "gmii_gmac1_grp", + .pins = gmii_gmac1_3516_pins, + .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), + /* Bring out RGMII on the GMAC1 pins */ + .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "pcigrp", @@ -1861,14 +1889,15 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { .name = "gpio2agrp", .pins = gpio2a_3516_pins, .num_pins = ARRAY_SIZE(gpio2a_3516_pins), - /* Conflict with GMII and extended parallel flash */ + .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, + /* Conflict with GMII GMAC1 and extended parallel flash */ }, { .name = "gpio2bgrp", .pins = gpio2b_3516_pins, .num_pins = ARRAY_SIZE(gpio2b_3516_pins), - /* Conflict with GMII, extended parallel flash and LCD */ - .mask = LCD_PADS_ENABLE, + /* Conflict with GMII GMAC1, extended parallel flash and LCD */ + .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, }, { .name = "gpio2cgrp", @@ -1971,7 +2000,7 @@ static const char * const icegrps[] = { "icegrp" }; static const char * const idegrps[] = { "idegrp" }; static const char * const satagrps[] = { "satagrp" }; static const char * const usbgrps[] = { "usbgrp" }; -static const char * const gmiigrps[] = { "gmiigrp" }; +static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" }; static const char * const pcigrps[] = { "pcigrp" }; static const char * const lpcgrps[] = { "lpcgrp" }; static const char * const lcdgrps[] = { "lcdgrp" };