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[209.132.180.67]) by mx.google.com with ESMTP id w19-v6si1158711pgl.278.2018.11.07.09.49.18; Wed, 07 Nov 2018 09:49:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VwwAthh0; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387800AbeKHDUn (ORCPT + 5 others); Wed, 7 Nov 2018 22:20:43 -0500 Received: from mail-pg1-f195.google.com ([209.85.215.195]:46120 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387793AbeKHDUn (ORCPT ); Wed, 7 Nov 2018 22:20:43 -0500 Received: by mail-pg1-f195.google.com with SMTP id w7so7601762pgp.13 for ; Wed, 07 Nov 2018 09:49:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v+EkBGJYgP5l8roNkAIcHxwpqxLvNbg8+WmAulqw8rE=; b=VwwAthh0B85ajA9GkQEvFwNHX72Ayd9FtzHG+fDvqnViLraYeRrrsynDx7f/L1s4hr rBi755aMl/HGQsuKBfw8SxOQIIcpoGhjNvwDXjnpumE1JLpY5vGmhqQBFxjFskFWApjb bp3NhxA2PaROm+FgrP+2/C5oecq1KR46uJNiA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v+EkBGJYgP5l8roNkAIcHxwpqxLvNbg8+WmAulqw8rE=; b=NpahZj9nV0vkUGSuKvBgIDT0GHSx2SeG9/tHvgUSY+LHlNoAHKGCi3C397b1elLPBX GnwrPWQgMXCmbkK/BuE4uNE+ixDjsVLix7OhRHG27K1tRMV1dAJhthIybVii1VbvSCLp C0htaR1WeHWFPUFxt2jd0/KC5llfSLPir5K+sIq/fpREz5NCT8DdGUL3hU5JImY29woA 4aC8Z+dwt/bSddGBuVx/s9HEaGhJ2YoW96a7xH9onFK8UlqZzNege51QLLrmi6OfBI9S qVTaHDb/7GUsCTb+IaKHjHXPpw1g4R8LRIAxiy4z36fohL/L2MVlMl33oq2el+nobdoN 7pbw== X-Gm-Message-State: AGRZ1gK05fgF/35w7HAAEWr3lAjiO8eQKW9CuHG2X96lX3ICE6k6exP6 xR5zdmBSZ3xT545VnVYhRSZa X-Received: by 2002:a63:4d66:: with SMTP id n38mr984121pgl.270.1541612956699; Wed, 07 Nov 2018 09:49:16 -0800 (PST) Received: from localhost.localdomain ([2409:4072:6282:6ca8:a0d9:6a81:97fe:992e]) by smtp.gmail.com with ESMTPSA id e70-v6sm1232645pfb.113.2018.11.07.09.49.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Nov 2018 09:49:16 -0800 (PST) From: Manivannan Sadhasivam To: sean.wang@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com, robh+dt@kernel.org Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, amit.kucheria@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 3/4] arm64: dts: mediatek: x20: Add pinmux support for UART1 Date: Wed, 7 Nov 2018 23:18:43 +0530 Message-Id: <20181107174844.5381-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181107174844.5381-1-manivannan.sadhasivam@linaro.org> References: <20181107174844.5381-1-manivannan.sadhasivam@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinmux support for UART1 on MediatekX20 Development board based on Mediatek MT6797 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 2 ++ arch/arm64/boot/dts/mediatek/mt6797.dtsi | 7 +++++++ 2 files changed, 9 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts index 742938a1a548..13939d55b85b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -30,4 +30,6 @@ &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 231230d32d09..a64bb84bdec3 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -141,6 +141,13 @@ "iocfgr", "iocfgt"; gpio-controller; #gpio-cells = <2>; + + uart1_pins_a: uart1 { + pins1 { + pinmux = , + ; + }; + }; }; scpsys: scpsys@10006000 {