[v1,1/3] gpio: mpc8xxx: support fsl-layerscape platform.

diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index 1dfd22522c..466f5f50cf 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -12,6 +12,8 @@ 
 #include <dm.h>
 #include <mapmem.h>
 #include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm/of_access.h>
 
 struct ccsr_gpio {
 	u32	gpdir;
@@ -20,6 +22,7 @@  struct ccsr_gpio {
 	u32	gpier;
 	u32	gpimr;
 	u32	gpicr;
+	u32	gpibe;
 };
 
 struct mpc8xxx_gpio_data {
@@ -49,31 +52,51 @@  inline u32 gpio_mask(uint gpio)
 
 static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdat) & mask;
+#else
 	return in_be32(&base->gpdat) & mask;
+#endif
 }
 
 static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpdir) & mask;
+#else
 	return in_be32(&base->gpdir) & mask;
+#endif
 }
 
 static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
 {
+#if CONFIG_ARM
+	return in_le32(&base->gpodr) & mask;
+#else
 	return in_be32(&base->gpodr) & mask;
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
 					      gpios)
 {
+#if CONFIG_ARM
+	setbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 1 -> open drain on */
 	setbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
 					       u32 gpios)
 {
+#if CONFIG_ARM
+	clrbits_le32(&base->gpodr, gpios);
+#else
 	/* GPODR register 0 -> open drain off (actively driven) */
 	clrbits_be32(&base->gpodr, gpios);
+#endif
 }
 
 static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
@@ -81,9 +104,13 @@  static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	u32 mask = gpio_mask(gpio);
 
+#if CONFIG_ARM
+	clrbits_le32(&data->base->gpdir, mask);
+#else
 	/* GPDIR register 0 -> input */
 	clrbits_be32(&data->base->gpdir, mask);
 
+#endif
 	return 0;
 }
 
@@ -100,10 +127,19 @@  static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
 		data->dat_shadow &= ~mask;
 	}
 
+#if CONFIG_ARM
+	gpdir = in_le32(&base->gpdir);
+#else
 	gpdir = in_be32(&base->gpdir);
+#endif
 	gpdir |= gpio_mask(gpio);
+#if CONFIG_ARM
+	out_le32(&base->gpdat, gpdir & data->dat_shadow);
+	out_le32(&base->gpdir, gpdir);
+#else
 	out_be32(&base->gpdat, gpdir & data->dat_shadow);
 	out_be32(&base->gpdir, gpdir);
+#endif
 
 	return 0;
 }
@@ -147,13 +183,29 @@  static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
 {
 	struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
 	fdt_addr_t addr;
+	u32 i;
+#if CONFIG_ARM
+	u32 reg[4];
+
+	dev_read_u32_array(dev, "reg", reg, 4);
+#else
 	u32 reg[2];
 
 	dev_read_u32_array(dev, "reg", reg, 2);
+#endif
+
+#if CONFIG_ARM
+	for (i = 0; i < 2; i++)
+		reg[i] = be32_to_cpu(reg[i]);
+#endif
 	addr = dev_translate_address(dev, reg);
 
 	plat->addr = addr;
+#if CONFIG_ARM
+	plat->size = reg[3];
+#else
 	plat->size = reg[1];
+#endif
 	plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
 
 	return 0;
@@ -187,6 +239,7 @@  static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
 static int mpc8xxx_gpio_probe(struct udevice *dev)
 {
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct device_node const  *np = dev->node.np;
 	struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
 	char name[32], *str;
 
@@ -198,6 +251,12 @@  static int mpc8xxx_gpio_probe(struct udevice *dev)
 	if (!str)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(np, "fsl,qoriq-gpio", NULL, NULL)) {
+		unsigned long gpibe = data->addr + sizeof(struct ccsr_gpio);
+
+		out_be32(gpibe, 0xffffffff);
+	}
+
 	uc_priv->bank_name = str;
 	uc_priv->gpio_count = data->gpio_count;