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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id c4sm16057511pfo.2.2021.03.02.19.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 19:31:26 -0800 (PST) From: Shawn Guo To: Bjorn Andersson Cc: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Shawn Guo , Vinod Koul Subject: [PATCH 4/4] arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges' Date: Wed, 3 Mar 2021 11:31:06 +0800 Message-Id: <20210303033106.549-5-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210303033106.549-1-shawn.guo@linaro.org> References: <20210303033106.549-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Cc: Vinod Koul Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 5ef460458f5c..fab211298c35 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -382,7 +382,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 203>; + gpio-ranges = <&tlmm 0 0 204>; qup_uart3_default_state: qup-uart3-default-state { rx {