diff mbox series

[v3] dt-bindings: gpio: stp: convert to json-schema

Message ID 20210523173910.661598-1-olek2@wp.pl
State Superseded
Headers show
Series [v3] dt-bindings: gpio: stp: convert to json-schema | expand

Commit Message

Aleksander Bajkowski May 23, 2021, 5:39 p.m. UTC
Convert the Lantiq STP Device Tree binding documentation to json-schema.
Add the missing pinctrl property to the example. Add missing lantiq,phy3
and lantiq,phy4 bindings for xRX300 and xRX330 SoCs.

Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
Changes since v2:
 - Changed phy numbering in description of pattern Properties. Numbering
   should start with 1. 
Changes since v1:
 - Renamed node to gpio.
 - Dropped default pinctrl from this binding.
 - Converted lantiq,phyX to patternProperties.
---
 .../bindings/gpio/gpio-stp-xway.txt           |  42 --------
 .../bindings/gpio/gpio-stp-xway.yaml          | 101 ++++++++++++++++++
 2 files changed, 101 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml

Comments

Linus Walleij May 27, 2021, 2:59 p.m. UTC | #1
On Sun, May 23, 2021 at 7:39 PM Aleksander Jan Bajkowski <olek2@wp.pl> wrote:

> Convert the Lantiq STP Device Tree binding documentation to json-schema.

> Add the missing pinctrl property to the example. Add missing lantiq,phy3

> and lantiq,phy4 bindings for xRX300 and xRX330 SoCs.

>

> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>


Acked-by: Linus Walleij <linus.walleij@linaro.org>


Yours,
Linus Walleij
Rob Herring June 2, 2021, 6:56 p.m. UTC | #2
On Sun, May 23, 2021 at 07:39:10PM +0200, Aleksander Jan Bajkowski wrote:
> Convert the Lantiq STP Device Tree binding documentation to json-schema.

> Add the missing pinctrl property to the example. Add missing lantiq,phy3

> and lantiq,phy4 bindings for xRX300 and xRX330 SoCs.

> 

> Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>

> ---

> Changes since v2:

>  - Changed phy numbering in description of pattern Properties. Numbering

>    should start with 1. 

> Changes since v1:

>  - Renamed node to gpio.

>  - Dropped default pinctrl from this binding.

>  - Converted lantiq,phyX to patternProperties.

> ---

>  .../bindings/gpio/gpio-stp-xway.txt           |  42 --------

>  .../bindings/gpio/gpio-stp-xway.yaml          | 101 ++++++++++++++++++

>  2 files changed, 101 insertions(+), 42 deletions(-)

>  delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt

>  create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml

> 

> diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt

> deleted file mode 100644

> index 78458adbf4b7..000000000000

> --- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt

> +++ /dev/null

> @@ -1,42 +0,0 @@

> -Lantiq SoC Serial To Parallel (STP) GPIO controller

> -

> -The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a

> -peripheral controller used to drive external shift register cascades. At most

> -3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem

> -to drive the 2 LSBs of the cascade automatically.

> -

> -

> -Required properties:

> -- compatible : Should be "lantiq,gpio-stp-xway"

> -- reg : Address and length of the register set for the device

> -- #gpio-cells : Should be two.  The first cell is the pin number and

> -  the second cell is used to specify optional parameters (currently

> -  unused).

> -- gpio-controller : Marks the device node as a gpio controller.

> -

> -Optional properties:

> -- lantiq,shadow : The default value that we shall assume as already set on the

> -  shift register cascade.

> -- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled

> -  in the shift register cascade.

> -- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit

> -  property can enable this feature.

> -- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.

> -- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.

> -- lantiq,rising : use rising instead of falling edge for the shift register

> -

> -Example:

> -

> -gpio1: stp@e100bb0 {

> -	compatible = "lantiq,gpio-stp-xway";

> -	reg = <0xE100BB0 0x40>;

> -	#gpio-cells = <2>;

> -	gpio-controller;

> -

> -	lantiq,shadow = <0xffff>;

> -	lantiq,groups = <0x7>;

> -	lantiq,dsl = <0x3>;

> -	lantiq,phy1 = <0x7>;

> -	lantiq,phy2 = <0x7>;

> -	/* lantiq,rising; */

> -};

> diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml

> new file mode 100644

> index 000000000000..7d817d84c434

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml

> @@ -0,0 +1,101 @@

> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

> +%YAML 1.2

> +---

> +$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#

> +$schema: http://devicetree.org/meta-schemas/core.yaml#

> +

> +title: Lantiq SoC Serial To Parallel (STP) GPIO controller

> +

> +description: |

> +  The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a

> +  peripheral controller used to drive external shift register cascades. At most

> +  3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem

> +  and Ethernet PHYs to drive some bytes of the cascade automatically.

> +

> +maintainers:

> +  - John Crispin <john@phrozen.org>

> +

> +properties:

> +  $nodename:

> +    pattern: "^gpio@[0-9a-f]+$"

> +

> +  compatible:

> +    const: lantiq,gpio-stp-xway

> +

> +  reg:

> +    description:

> +      Address and length of the register set for the device.


Drop. Don't need generic descriptions.

> +    maxItems: 1

> +

> +  gpio-controller: true

> +

> +  "#gpio-cells":

> +    description:

> +      The first cell is the pin number and the second cell is used to specify

> +      consumer flags.

> +    const: 2

> +

> +  lantiq,shadow:

> +    description:

> +      The default value that we shall assume as already set on the

> +      shift register cascade.

> +    $ref: /schemas/types.yaml#/definitions/uint32

> +    minimum: 0x000000

> +    maximum: 0xffffff

> +

> +  lantiq,groups:

> +    description:

> +      Set the 3 bit mask to select which of the 3 groups are enabled

> +      in the shift register cascade.

> +    $ref: /schemas/types.yaml#/definitions/uint32

> +    minimum: 0x0

> +    maximum: 0x7

> +

> +  lantiq,dsl:

> +    description:

> +      The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit

> +      property can enable this feature.

> +    $ref: /schemas/types.yaml#/definitions/uint32

> +    minimum: 0x0

> +    maximum: 0x3

> +

> +patternProperties:

> +  "lantiq,phy[1-4]":


"^lantiq,phy[1-4]$"

> +    description:

> +      The gphy core can control 3 bits of the gpio cascade. In the xRX200 family

> +      phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].

> +    $ref: /schemas/types.yaml#/definitions/uint32

> +    minimum: 0x0

> +    maximum: 0x7

> +

> +  lantiq,rising:


Not a pattern. Move to 'properties'.


> +    description:

> +      Use rising instead of falling edge for the shift register.

> +    type: boolean

> +

> +required:

> +  - compatible

> +  - reg

> +  - gpio-controller

> +  - "#gpio-cells"

> +

> +additionalProperties: false

> +

> +examples:

> +  - |

> +    gpio@e100bb0 {

> +        compatible = "lantiq,gpio-stp-xway";

> +        reg = <0xE100BB0 0x40>;

> +        #gpio-cells = <2>;

> +        gpio-controller;

> +

> +        pinctrl-0 = <&stp_pins>;

> +        pinctrl-names = "default";

> +

> +        lantiq,shadow = <0xffffff>;

> +        lantiq,groups = <0x7>;

> +        lantiq,dsl = <0x3>;

> +        lantiq,phy1 = <0x7>;

> +        lantiq,phy2 = <0x7>;

> +    };

> +...

> -- 

> 2.30.2
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
deleted file mode 100644
index 78458adbf4b7..000000000000
--- a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
+++ /dev/null
@@ -1,42 +0,0 @@ 
-Lantiq SoC Serial To Parallel (STP) GPIO controller
-
-The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
-peripheral controller used to drive external shift register cascades. At most
-3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
-to drive the 2 LSBs of the cascade automatically.
-
-
-Required properties:
-- compatible : Should be "lantiq,gpio-stp-xway"
-- reg : Address and length of the register set for the device
-- #gpio-cells : Should be two.  The first cell is the pin number and
-  the second cell is used to specify optional parameters (currently
-  unused).
-- gpio-controller : Marks the device node as a gpio controller.
-
-Optional properties:
-- lantiq,shadow : The default value that we shall assume as already set on the
-  shift register cascade.
-- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled
-  in the shift register cascade.
-- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
-  property can enable this feature.
-- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.
-- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.
-- lantiq,rising : use rising instead of falling edge for the shift register
-
-Example:
-
-gpio1: stp@e100bb0 {
-	compatible = "lantiq,gpio-stp-xway";
-	reg = <0xE100BB0 0x40>;
-	#gpio-cells = <2>;
-	gpio-controller;
-
-	lantiq,shadow = <0xffff>;
-	lantiq,groups = <0x7>;
-	lantiq,dsl = <0x3>;
-	lantiq,phy1 = <0x7>;
-	lantiq,phy2 = <0x7>;
-	/* lantiq,rising; */
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
new file mode 100644
index 000000000000..7d817d84c434
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-stp-xway.yaml
@@ -0,0 +1,101 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq SoC Serial To Parallel (STP) GPIO controller
+
+description: |
+  The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
+  peripheral controller used to drive external shift register cascades. At most
+  3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
+  and Ethernet PHYs to drive some bytes of the cascade automatically.
+
+maintainers:
+  - John Crispin <john@phrozen.org>
+
+properties:
+  $nodename:
+    pattern: "^gpio@[0-9a-f]+$"
+
+  compatible:
+    const: lantiq,gpio-stp-xway
+
+  reg:
+    description:
+      Address and length of the register set for the device.
+    maxItems: 1
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    description:
+      The first cell is the pin number and the second cell is used to specify
+      consumer flags.
+    const: 2
+
+  lantiq,shadow:
+    description:
+      The default value that we shall assume as already set on the
+      shift register cascade.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0x000000
+    maximum: 0xffffff
+
+  lantiq,groups:
+    description:
+      Set the 3 bit mask to select which of the 3 groups are enabled
+      in the shift register cascade.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0x0
+    maximum: 0x7
+
+  lantiq,dsl:
+    description:
+      The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
+      property can enable this feature.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0x0
+    maximum: 0x3
+
+patternProperties:
+  "lantiq,phy[1-4]":
+    description:
+      The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
+      phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
+    $ref: /schemas/types.yaml#/definitions/uint32
+    minimum: 0x0
+    maximum: 0x7
+
+  lantiq,rising:
+    description:
+      Use rising instead of falling edge for the shift register.
+    type: boolean
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio@e100bb0 {
+        compatible = "lantiq,gpio-stp-xway";
+        reg = <0xE100BB0 0x40>;
+        #gpio-cells = <2>;
+        gpio-controller;
+
+        pinctrl-0 = <&stp_pins>;
+        pinctrl-names = "default";
+
+        lantiq,shadow = <0xffffff>;
+        lantiq,groups = <0x7>;
+        lantiq,dsl = <0x3>;
+        lantiq,phy1 = <0x7>;
+        lantiq,phy2 = <0x7>;
+    };
+...