[v1,12/17] pinctrl: cy8c95x0: Implement ->pin_dbg_show()

Message ID	20220902182650.83098-12-andriy.shevchenko@linux.intel.com
State	Accepted
Commit	f12352f334c28a85e738f9caa31a0c5b07febd20
Headers	show Return-Path: <linux-gpio-owner@kernel.org> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> To: Linus Walleij <linus.walleij@linaro.org>, Andy Shevchenko <andriy.shevchenko@linux.intel.com>, Patrick Rudolph <patrick.rudolph@9elements.com>, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 12/17] pinctrl: cy8c95x0: Implement ->pin_dbg_show() Date: Fri, 2 Sep 2022 21:26:45 +0300 Message-Id: <20220902182650.83098-12-andriy.shevchenko@linux.intel.com> In-Reply-To: <20220902182650.83098-1-andriy.shevchenko@linux.intel.com> References: <20220902182650.83098-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	[v1,01/17] pinctrl: cy8c95x0: make irq_chip immutable \| expand [v1,01/17] pinctrl: cy8c95x0: make irq_chip immutable [v1,02/17] pinctrl: cy8c95x0: Allow IRQ chip core to handle numbering [v1,03/17] pinctrl: cy8c95x0: Allow most of the registers to be cached [v1,04/17] pinctrl: cy8c95x0: Fix return value in cy8c95x0_detect() [v1,05/17] pinctrl: cy8c95x0: Fix pin control name to enable more than one [v1,06/17] pinctrl: cy8c95x0: Drop unneeded npins assignment [v1,07/17] pinctrl: cy8c95x0: Enable GPIO range [v1,08/17] pinctrl: cy8c95x0: Remove device initialization [v1,09/17] pinctrl: cy8c95x0: Remove useless conditionals [v1,10/17] pinctrl: cy8c95x0: Remove custom ->set_config() [v1,11/17] pinctrl: cy8c95x0: Use 'default' in all switch-cases [v1,12/17] pinctrl: cy8c95x0: Implement ->pin_dbg_show() [v1,13/17] pinctrl: cy8c95x0: Make use of device properties [v1,14/17] pinctrl: cy8c95x0: support ACPI device found on Galileo Gen1 [v1,15/17] pinctrl: cy8c95x0: Override IRQ for one of the expanders on Galileo Gen 1 [v1,16/17] pinctrl: cy8c95x0: use bits.h macros for all masks [v1,17/17] pinctrl: cy8c95x0: Correct comment style

Message ID

20220902182650.83098-12-andriy.shevchenko@linux.intel.com

State

Accepted

Commit

f12352f334c28a85e738f9caa31a0c5b07febd20

Headers

From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Linus Walleij <linus.walleij@linaro.org>,
        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        Patrick Rudolph <patrick.rudolph@9elements.com>,
        linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v1 12/17] pinctrl: cy8c95x0: Implement ->pin_dbg_show()
Date: Fri,  2 Sep 2022 21:26:45 +0300
Message-Id: <20220902182650.83098-12-andriy.shevchenko@linux.intel.com>
In-Reply-To: <20220902182650.83098-1-andriy.shevchenko@linux.intel.com>
References: <20220902182650.83098-1-andriy.shevchenko@linux.intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

[v1,01/17] pinctrl: cy8c95x0: make irq_chip immutable | expand

Commit Message

Andy Shevchenko Sept. 2, 2022, 6:26 p.m. UTC

The introduced callback ->pin_dbg_show() is useful for debugging.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/pinctrl/pinctrl-cy8c95x0.c | 40 ++++++++++++++++++++++++------
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c
index 6fe442b44cab..ea81b5ae27a6 100644
--- a/drivers/pinctrl/pinctrl-cy8c95x0.c
+++ b/drivers/pinctrl/pinctrl-cy8c95x0.c
@@ -1010,25 +1010,49 @@  static int cy8c95x0_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 	return 0;
 }
 
+static const char *cy8c95x0_get_fname(unsigned int selector)
+{
+	if (selector == 0)
+		return "gpio";
+	else
+		return "pwm";
+}
+
+static void cy8c95x0_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+				  unsigned int pin)
+{
+	struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev);
+	DECLARE_BITMAP(mask, MAX_LINE);
+	DECLARE_BITMAP(pwm, MAX_LINE);
+
+	bitmap_zero(mask, MAX_LINE);
+	__set_bit(pin, mask);
+
+	if (cy8c95x0_read_regs_mask(chip, CY8C95X0_PWMSEL, pwm, mask)) {
+		seq_puts(s, "not available");
+		return;
+	}
+
+	seq_printf(s, "MODE:%s", cy8c95x0_get_fname(test_bit(pin, pwm)));
+}
+
 static const struct pinctrl_ops cy8c95x0_pinctrl_ops = {
 	.get_groups_count = cy8c95x0_pinctrl_get_groups_count,
 	.get_group_name = cy8c95x0_pinctrl_get_group_name,
 	.get_group_pins = cy8c95x0_pinctrl_get_group_pins,
 	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 	.dt_free_map = pinconf_generic_dt_free_map,
+	.pin_dbg_show = cy8c95x0_pin_dbg_show,
 };
 
-static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
+static const char *cy8c95x0_get_functions_name(struct pinctrl_dev *pctldev, unsigned int selector)
 {
-	return 2;
+	return cy8c95x0_get_fname(selector);
 }
 
-static const char *cy8c95x0_get_fname(struct pinctrl_dev *pctldev, unsigned int selector)
+static int cy8c95x0_get_functions_count(struct pinctrl_dev *pctldev)
 {
-	if (selector == 0)
-		return "gpio";
-	else
-		return "pwm";
+	return 2;
 }
 
 static int cy8c95x0_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
@@ -1077,7 +1101,7 @@  static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
 
 static const struct pinmux_ops cy8c95x0_pmxops = {
 	.get_functions_count = cy8c95x0_get_functions_count,
-	.get_function_name = cy8c95x0_get_fname,
+	.get_function_name = cy8c95x0_get_functions_name,
 	.get_function_groups = cy8c95x0_get_groups,
 	.set_mux = cy8c95x0_set_mux,
 	.strict = true,

[v1,12/17] pinctrl: cy8c95x0: Implement ->pin_dbg_show()

Commit Message

Patch