| Message ID | 20221221210917.458537-2-fabrizio.castro.jz@renesas.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Driver support for RZ/V2M PWC | expand |
Hi Fabrizio, On Wed, Dec 21, 2022 at 10:09 PM Fabrizio Castro <fabrizio.castro.jz@renesas.com> wrote: > The Renesas RZ/V2M External Power Sequence Controller (PWC) > IP is a multi-function device, and it's capable of: > * external power supply on/off sequence generation > * on/off signal generation for the LPDDR4 core power supply (LPVDD) > * key input signals processing > * general-purpose output pins > > Add the corresponding dt-bindings. > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > --- > > v1->v2: I have dropped syscon, simple-mfd, regmap, offset, and the child nodes. Thanks for the update! > --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/renesas,rzv2m-pwc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/V2M External Power Sequence Controller (PWC) > + > +description: |+ > + The PWC IP found in the RZ/V2M family of chips comes with the below > + capabilities > + - external power supply on/off sequence generation > + - on/off signal generation for the LPDDR4 core power supply (LPVDD) > + - key input signals processing > + - general-purpose output pins > + > +maintainers: > + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a09g011-pwc # RZ/V2M > + - renesas,r9a09g055-pwc # RZ/V2MA > + - const: renesas,rzv2m-pwc > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + renesas,rzv2m-pwc-power: > + description: The PWC is used to control the system power supplies. > + type: boolean I'm wondering if there is some other way to represent this, e.g. using DT topology? Some regulator relation? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for your feedback! > From: Geert Uytterhoeven <geert@linux-m68k.org> > Sent: 03 January 2023 08:29 > Subject: Re: [PATCH v2 1/4] dt-bindings: mfd: Add RZ/V2M PWC > > Hi Fabrizio, > > On Wed, Dec 21, 2022 at 10:09 PM Fabrizio Castro > <fabrizio.castro.jz@renesas.com> wrote: > > The Renesas RZ/V2M External Power Sequence Controller (PWC) > > IP is a multi-function device, and it's capable of: > > * external power supply on/off sequence generation > > * on/off signal generation for the LPDDR4 core power supply (LPVDD) > > * key input signals processing > > * general-purpose output pins > > > > Add the corresponding dt-bindings. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > > --- > > > > v1->v2: I have dropped syscon, simple-mfd, regmap, offset, and the child > nodes. > > Thanks for the update! > > > + renesas,rzv2m-pwc-power: > > + description: The PWC is used to control the system power supplies. > > + type: boolean > > I'm wondering if there is some other way to represent this, e.g. > using DT topology? Some regulator relation? Not that I can think of. With respect to power, this IP only generates control (enable) signals for external regulators, it does not supply power. Thanks, Fab > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But > when I'm talking to journalists I just say "programmer" or something like > that. > -- Linus Torvalds
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml new file mode 100644 index 000000000000..e6794c5152d5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,rzv2m-pwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc # RZ/V2M + - renesas,r9a09g055-pwc # RZ/V2MA + - const: renesas,rzv2m-pwc + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + renesas,rzv2m-pwc-power: + description: The PWC is used to control the system power supplies. + type: boolean + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; + reg = <0xa3700000 0x800>; + gpio-controller; + #gpio-cells = <2>; + renesas,rzv2m-pwc-power; + };
The Renesas RZ/V2M External Power Sequence Controller (PWC) IP is a multi-function device, and it's capable of: * external power supply on/off sequence generation * on/off signal generation for the LPDDR4 core power supply (LPVDD) * key input signals processing * general-purpose output pins Add the corresponding dt-bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> --- v1->v2: I have dropped syscon, simple-mfd, regmap, offset, and the child nodes. .../bindings/mfd/renesas,rzv2m-pwc.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml