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(162-227-164-7.lightspeed.sntcca.sbcglobal.net. [162.227.164.7]) by smtp.gmail.com with ESMTPSA id lr4-20020a17090b4b8400b002467717fa60sm23957pjb.16.2023.06.01.16.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jun 2023 16:02:05 -0700 (PDT) From: msmulski2@gmail.com To: linus.walleij@linaro.org Cc: brgl@bgdev.pl, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Michal Smulski Subject: [PATCH v2 1/1] gpio: mpc8xxx: latch GPIOs state on module load when configured as output Date: Thu, 1 Jun 2023 16:02:00 -0700 Message-Id: <20230601230200.6128-2-msmulski2@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230601230200.6128-1-msmulski2@gmail.com> References: <20230601230200.6128-1-msmulski2@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Michal Smulski Qoriq and related devices allow reading out state of GPIO set as output. However, currently on driver's init, all outputs are configured as driven low. So, any changes to GPIO confiuration will drive all pins (configured as output) as output-low. This patch latches state of output GPIOs before any GPIO configuration takes place. This preserves any output settings done prior to loading the driver (for example, by u-boot). Signed-off-by: Michal Smulski --- drivers/gpio/gpio-mpc8xxx.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mpc8xxx.c b/drivers/gpio/gpio-mpc8xxx.c index 3eb08cd1fdc0..6340e738c912 100644 --- a/drivers/gpio/gpio-mpc8xxx.c +++ b/drivers/gpio/gpio-mpc8xxx.c @@ -375,8 +375,12 @@ static int mpc8xxx_probe(struct platform_device *pdev) if (of_device_is_compatible(np, "fsl,qoriq-gpio") || of_device_is_compatible(np, "fsl,ls1028a-gpio") || of_device_is_compatible(np, "fsl,ls1088a-gpio") || - is_acpi_node(fwnode)) + is_acpi_node(fwnode)) { gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); + /* Also, latch state of GPIOs configured as output by bootloader. */ + gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & + gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); + } ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc); if (ret) {