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Tue, 20 Feb 2024 06:43:14 +0000 Received: from ZQ0PR01MB1302.CHNPR01.prod.partner.outlook.cn ([fe80::9d68:58f1:62cc:f1d3]) by ZQ0PR01MB1302.CHNPR01.prod.partner.outlook.cn ([fe80::9d68:58f1:62cc:f1d3%4]) with mapi id 15.20.7270.047; Tue, 20 Feb 2024 06:43:13 +0000 From: Alex Soo To: Linus Walleij , Bartosz Golaszewski , Hal Feng , Ley Foon Tan , Jianlong Huang , Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alex Soo Subject: [RFC PATCH v2 5/6] pinctrl: starfive: jh8100: add pinctrl driver for AON domain Date: Tue, 20 Feb 2024 14:42:45 +0800 Message-ID: <20240220064246.467216-6-yuklin.soo@starfivetech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240220064246.467216-1-yuklin.soo@starfivetech.com> References: <20240220064246.467216-1-yuklin.soo@starfivetech.com> X-ClientProxiedBy: BJXPR01CA0055.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:12::22) To ZQ0PR01MB1302.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:1b::9) Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1302:EE_|ZQ0PR01MB1239:EE_ X-MS-Office365-Filtering-Correlation-Id: 74c5e447-22b5-440d-80ba-08dc31df363a X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Alex Soo --- MAINTAINERS | 7 + drivers/pinctrl/starfive/Kconfig | 14 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jh8100-aon.c | 154 ++++++++++++++++++ .../starfive/pinctrl-starfive-jh8100.h | 4 + 5 files changed, 180 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c diff --git a/MAINTAINERS b/MAINTAINERS index beb219107d8c..fa8d2bbb4e47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20975,6 +20975,13 @@ S: Maintained F: drivers/reset/starfive/reset-starfive-jh81* F: include/dt-bindings/reset/starfive?jh81*.h +STARFIVE JH8100 PINCTRL DRIVERS +M: Alex Soo +S: Supported +F: Documentation/devicetree/bindings/pinctrl/starfive,jh81*.yaml +F: drivers/pinctrl/starfive/pinctrl-starfive-jh81* +F: include/dt-bindings/pinctrl/starfive,jh8100-pinctrl.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index bc123c0bf35e..6c448837f5f6 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -94,3 +94,17 @@ config PINCTRL_STARFIVE_JH8100_SYS_GMAC This provides syscon registers to indicate voltage level on SDIO1/GMAC1, to indicate GMAC1 pads voltage level under different GMAC interface modes, and to configure GMAC1 interface slew rate. + +config PINCTRL_STARFIVE_JH8100_AON + tristate "Always-on pinctrl and GPIO driver for the StarFive JH8100 SoC" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JH8100 + default ARCH_STARFIVE + help + Say yes here to support always-on pin control on the StarFive JH8100 SoC. + This provides an interface to the RGPIO pins not used by other peripherals + supporting inputs, outputs, configuring pull-up/pull-down and interrupts + on input changes. And also, the syscon registers to indicate voltage level + on eMMC/SDIO0/XSPI/RGPIOs/GMAC0, to indicate GMAC0 pads voltage level under + different GMAC interface modes, and to configure GMAC0 interface slew rate. diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index 236a693a8aef..46b1ab97779b 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH8100) += pinctrl-starfive-jh8100.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_EAST) += pinctrl-starfive-jh8100-sys-east.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_WEST) += pinctrl-starfive-jh8100-sys-west.o obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_SYS_GMAC) += pinctrl-starfive-jh8100-sys-gmac.o +obj-$(CONFIG_PINCTRL_STARFIVE_JH8100_AON) += pinctrl-starfive-jh8100-aon.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c new file mode 100644 index 000000000000..0f4a75f3c632 --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100-aon.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JH8100 SoC aon controller + * + * Copyright (C) 2023-2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include +#include +#include +#include + +#include + +#include "../core.h" +#include "../pinconf.h" +#include "../pinmux.h" +#include "pinctrl-starfive-jh8100.h" + +#define JH8100_AON_NGPIO 16 +#define JH8100_AON_GC_BASE 64 + +/* registers */ +#define JH8100_AON_DOEN 0x00 +#define JH8100_AON_DOUT 0x10 +#define JH8100_AON_GPI 0x20 +#define JH8100_AON_GPIOIN 0x54 + +#define JH8100_AON_GPIOEN 0x34 +#define JH8100_AON_GPIOIS 0x38 +#define JH8100_AON_GPIOIC 0x3c +#define JH8100_AON_GPIOIBE 0x40 +#define JH8100_AON_GPIOIEV 0x44 +#define JH8100_AON_GPIOIE 0x48 +#define JH8100_AON_GPIORIS 0x4c +#define JH8100_AON_GPIOMIS 0x50 + +static const struct pinctrl_pin_desc jh8100_aon_pins[] = { + PINCTRL_PIN(PAD_RGPIO0, "AON_RGPIO0"), + PINCTRL_PIN(PAD_RGPIO1, "AON_RGPIO1"), + PINCTRL_PIN(PAD_RGPIO2, "AON_RGPIO2"), + PINCTRL_PIN(PAD_RGPIO3, "AON_RGPIO3"), + PINCTRL_PIN(PAD_RGPIO4, "AON_RGPIO4"), + PINCTRL_PIN(PAD_RGPIO5, "AON_RGPIO5"), + PINCTRL_PIN(PAD_RGPIO6, "AON_RGPIO6"), + PINCTRL_PIN(PAD_RGPIO7, "AON_RGPIO7"), + PINCTRL_PIN(PAD_RGPIO8, "AON_RGPIO8"), + PINCTRL_PIN(PAD_RGPIO9, "AON_RGPIO9"), + PINCTRL_PIN(PAD_RGPIO10, "AON_RGPIO10"), + PINCTRL_PIN(PAD_RGPIO11, "AON_RGPIO11"), + PINCTRL_PIN(PAD_RGPIO12, "AON_RGPIO12"), + PINCTRL_PIN(PAD_RGPIO13, "AON_RGPIO13"), + PINCTRL_PIN(PAD_RGPIO14, "AON_RGPIO14"), + PINCTRL_PIN(PAD_RGPIO15, "AON_RGPIO15"), +}; + +#ifdef CONFIG_PM_SLEEP +static int jh8100_aon_pinctrl_suspend(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + if (device_may_wakeup(dev)) + enable_irq_wake(sfp->wakeup_irq); + + for (i = 0; i < sfp->info->nregs; i++) + sfp->jh8100_aon_regs[i] = readl_relaxed(sfp->base + (i * 4)); + + return pinctrl_force_sleep(sfp->pctl); +} + +static int jh8100_aon_pinctrl_resume(struct device *dev) +{ + struct jh8100_pinctrl *sfp; + int i; + + sfp = dev_get_drvdata(dev); + if (!sfp) + return -EINVAL; + + if (device_may_wakeup(dev)) + disable_irq_wake(sfp->wakeup_irq); + + for (i = 0; i < sfp->info->nregs; i++) + writel_relaxed(sfp->jh8100_aon_regs[i], sfp->base + (i * 4)); + + return pinctrl_force_default(sfp->pctl); +} +#endif + +static SIMPLE_DEV_PM_OPS(jh8100_aon_pinctrl_dev_pm_ops, + jh8100_aon_pinctrl_suspend, + jh8100_aon_pinctrl_resume); + +static const struct jh8100_gpio_irq_reg jh8100_aon_irq_reg = { + .is_reg_base = JH8100_AON_GPIOIS, + .ic_reg_base = JH8100_AON_GPIOIC, + .ibe_reg_base = JH8100_AON_GPIOIBE, + .iev_reg_base = JH8100_AON_GPIOIEV, + .ie_reg_base = JH8100_AON_GPIOIE, + .ris_reg_base = JH8100_AON_GPIORIS, + .mis_reg_base = JH8100_AON_GPIOMIS, + .ien_reg_base = JH8100_AON_GPIOEN, +}; + +static const struct jh8100_pinctrl_domain_info jh8100_aon_pinctrl_info = { + .pins = jh8100_aon_pins, + .npins = ARRAY_SIZE(jh8100_aon_pins), + .ngpios = JH8100_AON_NGPIO, + .gc_base = JH8100_AON_GC_BASE, + .name = JH8100_AON_DOMAIN_NAME, + .nregs = JH8100_AON_REG_NUM, + .dout_reg_base = JH8100_AON_DOUT, + .dout_mask = GENMASK(4, 0), + .doen_reg_base = JH8100_AON_DOEN, + .doen_mask = GENMASK(2, 0), + .gpi_reg_base = JH8100_AON_GPI, + .gpi_mask = GENMASK(4, 0), + .gpioin_reg_base = JH8100_AON_GPIOIN, + .irq_reg = &jh8100_aon_irq_reg, + .mis_pin_num = JH8100_AON_NGPIO +}; + +static const struct of_device_id jh8100_aon_pinctrl_of_match[] = { + { + .compatible = "starfive,jh8100-aon-pinctrl", + .data = &jh8100_aon_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh8100_aon_pinctrl_of_match); + +static struct platform_driver jh8100_aon_pinctrl_driver = { + .probe = jh8100_pinctrl_probe, + .driver = { + .name = "starfive-jh8100-aon-pinctrl", +#ifdef CONFIG_PM_SLEEP + .pm = &jh8100_aon_pinctrl_dev_pm_ops, +#endif + .of_match_table = jh8100_aon_pinctrl_of_match, + }, +}; +module_platform_driver(jh8100_aon_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JH8100 SoC aon controller"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h index 4652885feaa2..b4042a7f7936 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh8100.h @@ -16,13 +16,16 @@ #define JH8100_SYS_W_DOMAIN_NAME "jh8100-sys-west" #define JH8100_SYS_E_DOMAIN_NAME "jh8100-sys-east" #define JH8100_SYS_G_DOMAIN_NAME "jh8100-sys-gmac" +#define JH8100_AON_DOMAIN_NAME "jh8100-aon" #define JH8100_SYS_W_REG_NUM 44 #define JH8100_SYS_E_REG_NUM 116 #define JH8100_SYS_G_REG_NUM 19 +#define JH8100_AON_REG_NUM 65 #define JH8100_SYS_W_GPO_PDA_00_15_CFG 0x074 #define JH8100_SYS_E_GPO_PDA_00_47_CFG 0x114 +#define JH8100_AON_GPO_PDA_00_15_CFG 0x90 struct jh8100_pinctrl { struct device *dev; @@ -37,6 +40,7 @@ struct jh8100_pinctrl { unsigned int jh8100_sys_west_regs[JH8100_SYS_W_REG_NUM]; unsigned int jh8100_sys_east_regs[JH8100_SYS_E_REG_NUM]; unsigned int jh8100_sys_gmac_regs[JH8100_SYS_G_REG_NUM]; + unsigned int jh8100_aon_regs[JH8100_AON_REG_NUM]; /* wakeup */ int wakeup_gpio; int wakeup_irq;