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Tue, 16 Apr 2024 05:35:03 -0700 From: Prathamesh Shete To: , , , , , , CC: , , , , Subject: [PATCH] gpio: tegra186: Fix tegra186_gpio_is_accessible() check Date: Tue, 16 Apr 2024 18:05:01 +0530 Message-ID: <20240416123501.12916-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE3:EE_|CH2PR12MB4053:EE_ X-MS-Office365-Filtering-Correlation-Id: e2f5e69d-8940-4bb2-3480-08dc5e11a95c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Yasai6qY6TqUFE9fmNU3P/JdEH7RXHt3SJ2nXX1WftuIhsVRJvcPxTTjzfrqgBBEHp0h7OKPIytWu5nkqB5tNBDHlCmEc/lMNrBHvx+Yras5Xk/IgzodCJCEvoF4zsVNi/SPYMaFrkdcGys7d3DC1rzSq04DgV8PzO62jc4//K+arlJIYPkSl0vLwMs9ISOd8QiDc0Wqtx1PBDy+e2ilKNYdDZG0i28OVwrt7nhULPZRmHf3C82ZURDPvU7rfNfydEPOkT5GxaqDxjK6PB5pvFc1OhQQnMWUg8l6r8/ptaLo1nc09kkS4ggGy7upo+DwkbEN/BZsu+t+NAnzvBs+0u0NmjV06Y2ugKYJCC+jkrXs4/GmlRmcDR6tR7ZnNWNglH66erPC9DFI/B7+TnppTYacK/Uwp9D1wBS1ktn7u/NBY7lVGgXYQ9aXekuIAtBC7HzTm8BuyrS6Nzx286Abl9hkLS/LhqEuBTQeTQV9inGySquvY42DETqVXsPHwn0fBliSGk03ZifUf0cjfflrwgo29PxWX8d0zHeXF89yuc+jgDtyK1rPht2KmfIwTs5nw+oiHrkYdQSHw9ZqjXhZBYtT+HrXXFmZ0vfmEP5gSxs+EC42c0IyxALOeBJN2sM/pfiyQxnZgX3e0gt8nsuh0rjZwb1UwL31FEOkN91QlIcWveHqyD/lO4FSf8DBuPUg6Ril3wfz0gW4FK4qPw2YHvnsBgeyYEvdvMS58Emev42IGI5KyhctVAB/IaVC0FBb X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(376005)(1800799015)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 12:35:12.8458 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2f5e69d-8940-4bb2-3480-08dc5e11a95c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4053 The controller has several register bits describing access control information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it means we have full read/write access to all the registers for given GPIO pin. When SCR_SEC[R|W]EN is set, it means we need to further check the accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given GPIO pin. This check was previously declaring that a GPIO pin was accessible only if either of the following conditions were met: - SCR_SEC_REN + SCR_SEC_WEN both set or - SCR_SEC_REN + SCR_SEC_WEN both set and SCR_SEC_G1R + SCR_SEC_G1W both set Update the check to properly handle cases where only one of SCR_SEC_REN or SCR_SEC_WEN is set. Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before access.") Signed-off-by: Prathamesh Shete Acked-by: Thierry Reding --- drivers/gpio/gpio-tegra186.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index d87dd06db40d..54c8b02eec22 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -36,12 +36,10 @@ #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) -#define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN | \ - TEGRA186_GPIO_SCR_SEC_G1R | \ +#define TEGRA186_GPIO_READ_ACCESS (TEGRA186_GPIO_SCR_SEC_REN | \ + TEGRA186_GPIO_SCR_SEC_G1R) +#define TEGRA186_GPIO_WRITE_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ TEGRA186_GPIO_SCR_SEC_G1W) -#define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \ - TEGRA186_GPIO_SCR_SEC_REN) /* control registers */ #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 @@ -177,10 +175,18 @@ static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned value = __raw_readl(secure + TEGRA186_GPIO_SCR); - if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0) - return true; + /* + * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the + * registers for given GPIO pin. + * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying + * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given + * GPIO pin. + */ - if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS) + if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 || + (value & TEGRA186_GPIO_READ_ACCESS)) && + ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 || + (value & TEGRA186_GPIO_WRITE_ACCESS))) return true; return false;