From patchwork Tue Jun 18 12:08:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= X-Patchwork-Id: 805733 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B553013C684; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718712556; cv=none; b=BaxVPRSYOBOaAGAvmuCEbro8LBuH9KaINNXra1q1Rq13kkGHcuYRa4ZlmlO4Rv+SNqC3XvzpPmApCi74u6hjqNCOmZx3BhIavGJfBJVyrluRs6P3Xy1LohtTJjqnYppeRSq9sOuoHBLJPXlFeIKUY8LsUBFfiCxuONa4eC3dqQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718712556; c=relaxed/simple; bh=LWQPrf1FvAHGlJ3lnQwcoSykHCEJ8Ls1oovG0sX2X3E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gtDE2rNIHNXvo7SvS6OMivo0u6u+yao9pRiSTI7qf/ydTnAiVEcvhzja+y4nSpzsdnUlqksFXdD10jw1yQEZodKydl8N6XYXeGZY2t2ysyZXi6lWLQZdvcGNGlS9Md23gOtKgr0OgyVpTjiiH151BvgFtvedLNhuU/4VhkeCyCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Lra8iNF4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Lra8iNF4" Received: by smtp.kernel.org (Postfix) with ESMTPS id 80A58C4DDFC; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718712556; bh=LWQPrf1FvAHGlJ3lnQwcoSykHCEJ8Ls1oovG0sX2X3E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Lra8iNF4q7ZORsGtbr7NysAcrObR1R6O9RnQp0DR9vObiRtDGDCaXGeRPIpPiMvDH PH6stXxG+S2y8JvNMbBh5SEVH/M/v9ThvasWYrwL2qi+HhfJJ0kBnafDDN1E7xU8aI ypMlIEC2rtxeBFXU/4V+Te1w2QIP2gwcld8E3i5TxD8IWmo4oBFbP9/B8uPQKb+/CI Qh+Bft6zzFfKGEarQwJdbMRYGJ/kz3Mb9PDdLyE0EplUqc7JOoyqZmZoYrvtF+xFHx N09S/WaL0urljMi+/5Cn6kn9lqALjofw60TUEI6AyIDr38a3yI4h5PpMjUF9eqlsmx cv4B2Oz78fqxQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 751DFC2BBCA; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 18 Jun 2024 14:08:19 +0200 Subject: [PATCH RESEND v10 08/12] clk: mmp: Add Marvell PXA1908 MPMU driver Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240618-pxa1908-lkml-v10-8-754e5ece9078@skole.hr> References: <20240618-pxa1908-lkml-v10-0-754e5ece9078@skole.hr> In-Reply-To: <20240618-pxa1908-lkml-v10-0-754e5ece9078@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Tony Luck , "Guilherme G. Piccoli" , Rob Herring , Kees Cook Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4933; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=fyLW+E7x8AxGG21iMnrhiFTAVRNSublrbBTu9AUPdPE=; b=owEBbQKS/ZANAwAIAZoRnrBCLZbhAcsmYgBmcXjSglgCorvUGfnHAirEQrU7PERZWJ5CLULwe 6B3yDJ9YLuJAjMEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZnF40gAKCRCaEZ6wQi2W 4cYXD/44He6uNIZhpnezl0eoZ4XSZZOOo0xdy3UJXSTCpINNfTdvFqd5OtP2sHzQ+hL3eTBtc/g f0EzmfpPZHSHHWIgRL8ubkF+ZM6iFTpqaiH/8dqurXlO808mmaJIfsYP4W7Q08EotzhKk1uc3/0 TAxImFa8bhTlBWRyON2D/YMYJCjvnQd4gG9FeVq/DhR8d/X2+Zvl0CN20ni+qe231wTe1zWt8i1 tJXPr9v7f5MBmDuLt4A3ExAy8BPNtScPfVzKAanxkZEoNnNBTj9N/g6/6Q7ghFd4FXV7Z3+8cxf lAJkEB85f5BXjbX48JOg3xGUePODkocrs65tSQ7GTNV2K0wpIIgCUwMvokpOPxWTYHH4HjlFxON iLNkyA2f3KC4THQQneFgkd+W/02LqoZlRg+j5XQ/Pzmitaair/eLQ+x7ziE6LWW7h8bYyeWnOVw IbOsWXZOB36V4F3MiHOGyJiu7f1qQF6EwdZv3S9KQEF2RupPyApJJgG5HDP2WwUrJYXfqpiR9S7 614alC3A5cMuPz3heakhiwOQX5WFCRVSGAqFbVXLcAQUEZpJyXwgg42ewnDFnD2m4ZPBsUnD86U vdm69Q+bNMSFGTFgYhiTnCWij4H0lY4sFkRHuO1kknF/Lny+FpfwhIrRHKR9rfzS5zy8wJQ4BcQ hHj8t2FxMSHrKqw== X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/default with auth_id=112 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= Reply-To: duje.mihanovic@skole.hr From: Duje Mihanović Add driver for the MPMU controller block on Marvell's PXA1908 SoC. The driver is incomplete, currently only supporting the fixed PLL1; dynamic PLLs 2-4 and CPU/DDR/AXI clock support is missing. Signed-off-by: Duje Mihanović --- drivers/clk/mmp/Makefile | 2 +- drivers/clk/mmp/clk-pxa1908-mpmu.c | 112 +++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile index a8b1a4b08824..062cd87fa8dd 100644 --- a/drivers/clk/mmp/Makefile +++ b/drivers/clk/mmp/Makefile @@ -11,4 +11,4 @@ obj-$(CONFIG_MACH_MMP_DT) += clk-of-pxa168.o clk-of-pxa910.o obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o obj-$(CONFIG_COMMON_CLK_MMP2_AUDIO) += clk-audio.o -obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o +obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-pxa1908-apbc.o clk-pxa1908-apbcp.o clk-pxa1908-apmu.o clk-pxa1908-mpmu.o diff --git a/drivers/clk/mmp/clk-pxa1908-mpmu.c b/drivers/clk/mmp/clk-pxa1908-mpmu.c new file mode 100644 index 000000000000..e3337bacaadd --- /dev/null +++ b/drivers/clk/mmp/clk-pxa1908-mpmu.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +#include + +#include "clk.h" + +#define MPMU_UART_PLL 0x14 + +#define MPMU_NR_CLKS 39 + +struct pxa1908_clk_unit { + struct mmp_clk_unit unit; + void __iomem *base; +}; + +static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { + {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768}, + {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832 * HZ_PER_MHZ}, + {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248 * HZ_PER_MHZ}, +}; + +static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { + {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0}, + {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0}, + {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0}, + {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0}, + {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0}, + {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0}, + {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0}, + {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0}, + {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0}, + {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0}, + {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0}, + {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0}, + {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0}, +}; + +static struct u32_fract uart_factor_tbl[] = { + {.numerator = 8125, .denominator = 1536}, /* 14.745MHz */ +}; + +static struct mmp_clk_factor_masks uart_factor_masks = { + .factor = 2, + .num_mask = GENMASK(12, 0), + .den_mask = GENMASK(12, 0), + .num_shift = 16, + .den_shift = 0, +}; + +static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit) +{ + struct mmp_clk_unit *unit = &pxa_unit->unit; + + mmp_register_fixed_rate_clks(unit, fixed_rate_clks, + ARRAY_SIZE(fixed_rate_clks)); + + mmp_register_fixed_factor_clks(unit, fixed_factor_clks, + ARRAY_SIZE(fixed_factor_clks)); + + mmp_clk_register_factor("uart_pll", "pll1_d4", + CLK_SET_RATE_PARENT, + pxa_unit->base + MPMU_UART_PLL, + &uart_factor_masks, uart_factor_tbl, + ARRAY_SIZE(uart_factor_tbl), NULL); +} + +static int pxa1908_mpmu_probe(struct platform_device *pdev) +{ + struct pxa1908_clk_unit *pxa_unit; + + pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); + if (IS_ERR(pxa_unit)) + return PTR_ERR(pxa_unit); + + pxa_unit->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pxa_unit->base)) + return PTR_ERR(pxa_unit->base); + + mmp_clk_init(pdev->dev.of_node, &pxa_unit->unit, MPMU_NR_CLKS); + + pxa1908_pll_init(pxa_unit); + + return 0; +} + +static const struct of_device_id pxa1908_mpmu_match_table[] = { + { .compatible = "marvell,pxa1908-mpmu" }, + { } +}; +MODULE_DEVICE_TABLE(of, pxa1908_mpmu_match_table); + +static struct platform_driver pxa1908_mpmu_driver = { + .probe = pxa1908_mpmu_probe, + .driver = { + .name = "pxa1908-mpmu", + .of_match_table = pxa1908_mpmu_match_table + } +}; +module_platform_driver(pxa1908_mpmu_driver); + +MODULE_AUTHOR("Duje Mihanović "); +MODULE_DESCRIPTION("Marvell PXA1908 MPMU Clock Driver"); +MODULE_LICENSE("GPL");