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Thu, 12 Jun 2025 06:15:37 -0700 (PDT) Received: from [127.0.1.1] ([2a01:cb1d:dc:7e00:8b99:9926:3892:5310]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4532dea17d7sm20619795e9.10.2025.06.12.06.15.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jun 2025 06:15:37 -0700 (PDT) From: Bartosz Golaszewski Date: Thu, 12 Jun 2025 15:15:20 +0200 Subject: [PATCH 11/16] pinctrl: pic32: use new GPIO line value setter callbacks Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250612-gpiochip-set-rv-pinctrl-remaining-v1-11-556b0a530cd4@linaro.org> References: <20250612-gpiochip-set-rv-pinctrl-remaining-v1-0-556b0a530cd4@linaro.org> In-Reply-To: <20250612-gpiochip-set-rv-pinctrl-remaining-v1-0-556b0a530cd4@linaro.org> To: Dvorkin Dmitry , Wells Lu , Linus Walleij , Bartosz Golaszewski , Patrice Chotard , Support Opensource , Baruch Siach , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Viresh Kumar , Lakshmi Sowjanya D , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, soc@lists.linux.dev, linux-sunxi@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski --- drivers/pinctrl/pinctrl-pic32.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index bf827ab081a1d672c440a8b4eccab539fdc215e7..6d64cab97e8116625c2efce29a3e5db8248bcba4 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -1828,8 +1828,8 @@ static int pic32_gpio_get(struct gpio_chip *chip, unsigned offset) return !!(readl(bank->reg_base + PORT_REG) & BIT(offset)); } -static void pic32_gpio_set(struct gpio_chip *chip, unsigned offset, - int value) +static int pic32_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct pic32_gpio_bank *bank = gpiochip_get_data(chip); u32 mask = BIT(offset); @@ -1838,6 +1838,8 @@ static void pic32_gpio_set(struct gpio_chip *chip, unsigned offset, writel(mask, bank->reg_base + PIC32_SET(PORT_REG)); else writel(mask, bank->reg_base + PIC32_CLR(PORT_REG)); + + return 0; } static int pic32_gpio_direction_output(struct gpio_chip *chip, @@ -2118,7 +2120,7 @@ static void pic32_gpio_irq_handler(struct irq_desc *desc) .direction_input = pic32_gpio_direction_input, \ .direction_output = pic32_gpio_direction_output, \ .get = pic32_gpio_get, \ - .set = pic32_gpio_set, \ + .set_rv = pic32_gpio_set, \ .ngpio = _npins, \ .base = GPIO_BANK_START(_bank), \ .owner = THIS_MODULE, \