From patchwork Fri Jun 13 10:14:17 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Patchwork-Id: 896313 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACE2626B746; Fri, 13 Jun 2025 10:16:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749809790; cv=none; b=SocGFIWSgZ5Ie1KvXQEvOfBq8IbQlwNWbXZtb2lFtnUBHyJQRZP//nmXTJuhOfmggeaHS0QhIBFDI6RoqeFrbF+L++ROMDmNo6FwzUNNNfCkn2zliamTyhnbyl+L6tQ1S4gbtqRPSnhAMyPBdhfX2d3tjL5nL+y62xjRZqFGHNU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749809790; c=relaxed/simple; bh=lndg55ulgwz6N3tlL/yuiVojWKk/upndGowO0ds+dBM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=OBydEAW50X54omJspOyPRkObudJrVH2FQoMwIsaWvRK1Aph4jzCy06DCyJBMZ1HazIWwZk10cGpDXOepyl/sgDLM1LlGmZF+1CxqEcrL3MUB60Z9vvDrnj6HnaerbEuVDvtZeEOZMkbYIS1qrvR6nXgJcD35F3ktEN9QOiM/v8w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=ohQeI3bx; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="ohQeI3bx" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55D9SlWh003048; Fri, 13 Jun 2025 12:16:16 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= dqAz444oyv1tNExXQ6LB+NGBTHbnGCQW3fM6rAo+GF0=; b=ohQeI3bxVkreqjGT 34N9nhR41a0f1tBVInsWw9zJHHPSfXI1NxWIJPxHL3cDWPbOQm/Barzp97TnkzmM nDKT3uzr/Mh8k+Qdv5Zax/8Cuxn/ukS1QInImq0jZa98Rp43rTnLNDHpR0do5B03 fkYzpJxXlzS1PAEYtOvhVjKs8C61f3Kouuj9g5i6tFl/kmn8pNDxjbUoWvp9pLLC 12o6Z2vKGTnoUf8C2ksZa5J1bFyyF9iOL4Mt6Wbd0tX7URtf5EvLvWoBFIZBWJ8B PZW1ZGy8B5AvmSEtBJKCUYPMuEFhE6tsn6nXMFkwkcPuv8b4gU3wYM/vufCPdye4 37RMfw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 474y05jqsf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Jun 2025 12:16:16 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 35C614005C; Fri, 13 Jun 2025 12:15:05 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D2DF938C44E; Fri, 13 Jun 2025 12:14:21 +0200 (CEST) Received: from localhost (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 13 Jun 2025 12:14:21 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Fri, 13 Jun 2025 12:14:17 +0200 Subject: [PATCH v5 6/9] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp15 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250613-hdp-upstream-v5-6-6fd6f0dc527c@foss.st.com> References: <20250613-hdp-upstream-v5-0-6fd6f0dc527c@foss.st.com> In-Reply-To: <20250613-hdp-upstream-v5-0-6fd6f0dc527c@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-0537a X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-12_10,2025-06-12_02,2025-03-28_01 Add the hdp devicetree node for stm32mp15 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic --- arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 0daa8ffe2ff5..b1b568dfd126 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -270,6 +270,13 @@ dts: thermal@50028000 { status = "disabled"; }; + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp151-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma1: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>;