From patchwork Fri Jun 13 03:29:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 896319 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D41B2571BA; Fri, 13 Jun 2025 03:30:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785417; cv=none; b=GwZH0DA4xK0pChQBCm+nORZJm0adjiYUHHeuLhevsmtURFilMsj9LvYgt9AgrGKxlUzSJZkQbV+yNL1nbpX31JM7jat4R3NySeVfbeSVhWjZ+7fb55qkfCav9vmdl8FOmfMUr1mq5deqnOaDhoTbyuDRQXmyiTxw3rjEKZifuTk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749785417; c=relaxed/simple; bh=hY26OLd+ttBIhv3LwxsuAVeB6IQrJnV8zG6jeGobekI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Om2vv2J9hN0EdHGirHEZ+rxh6ls2b9oCf14h5+fumFqYcjqPFS5FIdJyRUIIjzRSLX/hxhgaJmzwT9DO+z4H7tuwJmqnywtBwNyAMSZjw5d1GWz8eQ/rfwkqb04bJbE/lnc0bm/vuyba4UXi7nPgqmfAHuX4wORfmw4FBlKII0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 13 Jun 2025 11:30:02 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 13 Jun 2025 11:30:02 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH 5/7] ARM: dts: aspeed-g6: Add PCIe RC node Date: Fri, 13 Jun 2025 11:29:59 +0800 Message-ID: <20250613033001.3153637-6-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The AST2600 has one PCIe RC, and add the relative configure regmap. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 8ed715bd53aa..d46a151e3c99 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -379,6 +379,59 @@ rng: hwrng@1e6e2524 { quality = <100>; }; + pcie_phy1: pcie-phy@1e6ed200 { + compatible = "aspeed,ast2600-pcie-phy", "syscon"; + reg = <0x1e6ed200 0x100>; + }; + + pcie_cfg: pcie-cfg@1e770000 { + compatible = "aspeed,ast2600-pcie-cfg", "syscon"; + reg = <0x1e770000 0x80>; + }; + + pcie0: pcie@1e7700c0 { + compatible = "aspeed,ast2600-pcie"; + device_type = "pci"; + reg = <0x1e7700c0 0x40>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x80 0xff>; + + ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 + 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>; + + status = "disabled"; + + resets = <&syscon ASPEED_RESET_H2X>, + <&syscon ASPEED_RESET_PCIE_RC_O>; + reset-names = "h2x", "perst"; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcierc1_default>; + + #interrupt-cells = <1>; + msi-parent = <&pcie0>; + msi-controller; + msi_address = <0x1e77005c>; + + aspeed,ahbc = <&ahbc>; + aspeed,pciecfg = <&pcie_cfg>; + aspeed,pciephy = <&pcie_phy1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + gfx: display@1e6e6000 { compatible = "aspeed,ast2600-gfx", "syscon"; reg = <0x1e6e6000 0x1000>;