From patchwork Fri Jun 20 09:40:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Darren.Ye" X-Patchwork-Id: 898492 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3F722882A8; Fri, 20 Jun 2025 09:42:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750412534; cv=none; b=CNrfXN9W/a9/7yI3YtNo2cgEysuvZb1vCKvqN1BS8WT2wvfEtFtgwn3vItoEalQn7XJG7qYa/M+gdrRNTBAzdhAr9HHVCB34OOI/oPNTSYjHizT2/HVIarDPbavO44BqwE0RQCpSxa5rAre56yJMCbsplvbA2d+8+Oj2fuZVURs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750412534; c=relaxed/simple; bh=rvF3mA8p1qAhXv+QwA5KoTtZat0yYULRLNXyFWv6atc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pnz/tx0Z0Qw7DHokBWampP4NsJ6odNs/2xOgPMshPF3VUXzzcPnD/fXsCVah4kzzJFFHAtMVAUTdkTrP7dZ18GgeG4fQQeG+jhC/0XyIPo1RFiPUV2SNYNOHMHDS69lZiNGaArxhjB2Z6FL9fVPx15EQoKvrUNzttttSryfs540= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=iPj5YsEN; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iPj5YsEN" X-UUID: d2ff1c084dba11f0b33aeb1e7f16c2b6-20250620 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=lMiUbP+aC6CKVSwU+3SgtZe+5nQE7rMAf5Q4NZyTgkI=; b=iPj5YsENycYb0ejYZoY8+YJKy3P1e4oXRYjaqIlm3Ie/ny0/PFxTDKEWdxULiKs5i4sfPuwYpKJZTZEQivvgQXENY9Q1tDQ+rQJZyvt8+vaK6RcCMA451FoGdnWzbccvQXvBPLFh5TrMxJEwdM3y0LMZTUA8TA3OzSc01bCo90I=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.3, REQID:858d6d0b-4869-4c6f-9700-9c8b90f823ff, IP:0, UR L:25,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:20 X-CID-META: VersionHash:09905cf, CLOUDID:4faee658-abad-4ac2-9923-3af0a8a9a079, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|97|99|83|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: d2ff1c084dba11f0b33aeb1e7f16c2b6-20250620 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 775142842; Fri, 20 Jun 2025 17:42:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 20 Jun 2025 17:42:02 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 20 Jun 2025 17:42:01 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye , Krzysztof Kozlowski Subject: [PATCH v5 08/10] ASoC: dt-bindings: mediatek, mt8196-afe: add support for MT8196 audio AFE controller Date: Fri, 20 Jun 2025 17:40:41 +0800 Message-ID: <20250620094140.11093-9-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250620094140.11093-1-darren.ye@mediatek.com> References: <20250620094140.11093-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Darren Ye This patch adds initial support for the audio AFE(Audio Front End) controller on the mediatek MT8196 platform. Signed-off-by: Darren Ye Reviewed-by: Krzysztof Kozlowski --- .../bindings/sound/mediatek,mt8196-afe.yaml | 157 ++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml new file mode 100644 index 000000000000..fe147eddf5e7 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Audio Front End PCM controller for MT8196 + +maintainers: + - Darren Ye + +properties: + compatible: + const: mediatek,mt8196-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + + mediatek,vlpcksys: + $ref: /schemas/types.yaml#/definitions/phandle + description: To set up the apll12 tuner + + power-domains: + maxItems: 1 + + clocks: + items: + - description: mux for audio intbus + - description: mux for audio engen1 + - description: mux for audio engen2 + - description: mux for audio h + - description: vlp 26m clock + - description: audio apll1 clock + - description: audio apll2 clock + - description: audio apll1 divide4 + - description: audio apll2 divide4 + - description: audio apll12 divide for i2sin0 + - description: audio apll12 divide for i2sin1 + - description: audio apll12 divide for fmi2s + - description: audio apll12 divide for tdmout mck + - description: audio apll12 divide for tdmout bck + - description: mux for audio apll1 + - description: mux for audio apll2 + - description: mux for i2sin0 mck + - description: mux for i2sin1 mck + - description: mux for fmi2s mck + - description: mux for tdmout mck + - description: mux for adsp clock + - description: 26m clock + + clock-names: + items: + - const: top_aud_intbus + - const: top_aud_eng1 + - const: top_aud_eng2 + - const: top_aud_h + - const: vlp_clk26m + - const: apll1 + - const: apll2 + - const: apll1_d4 + - const: apll2_d4 + - const: apll12_div_i2sin0 + - const: apll12_div_i2sin1 + - const: apll12_div_fmi2s + - const: apll12_div_tdmout_m + - const: apll12_div_tdmout_b + - const: top_apll1 + - const: top_apll2 + - const: top_i2sin0 + - const: top_i2sin1 + - const: top_fmi2s + - const: top_tdmout + - const: top_adsp + - const: clk26m + +required: + - compatible + - reg + - interrupts + - memory-region + - mediatek,vlpcksys + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + afe@1a110000 { + compatible = "mediatek,mt8196-afe"; + reg = <0 0x1a110000 0 0x9000>; + interrupts = ; + memory-region = <&afe_dma_mem_reserved>; + mediatek,vlpcksys = <&vlp_cksys_clk>; + power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO + clocks = <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL + <&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL + <&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL + <&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL + <&vlp_cksys_clk 45>, //CLK_VLP_CK_CLKSQ + <&cksys_clk 129>, //CLK_CK_APLL1 + <&cksys_clk 132>, //CLK_CK_APLL2 + <&cksys_clk 130>, //CLK_CK_APLL1_D4 + <&cksys_clk 133>, //CLK_CK_APLL2_D4 + <&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0 + <&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1 + <&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S + <&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M + <&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B + <&cksys_clk 43>, //CLK_CK_AUD_1_SEL + <&cksys_clk 44>, //CLK_CK_AUD_2_SEL + <&cksys_clk 66>, //CLK_CK_APLL_I2SIN0_MCK_SEL + <&cksys_clk 67>, //CLK_CK_APLL_I2SIN1_MCK_SEL + <&cksys_clk 78>, //CLK_CK_APLL_FMI2S_MCK_SEL + <&cksys_clk 79>, //CLK_CK_APLL_TDMOUT_MCK_SEL + <&cksys_clk 45>, //CLK_CK_ADSP_SEL + <&cksys_clk 140>; //CLK_CK_TCK_26M_MX9 + clock-names = "top_aud_intbus", + "top_aud_eng1", + "top_aud_eng2", + "top_aud_h", + "vlp_clk26m", + "apll1", + "apll2", + "apll1_d4", + "apll2_d4", + "apll12_div_i2sin0", + "apll12_div_i2sin1", + "apll12_div_fmi2s", + "apll12_div_tdmout_m", + "apll12_div_tdmout_b", + "top_apll1", + "top_apll2", + "top_i2sin0", + "top_i2sin1", + "top_fmi2s", + "top_tdmout", + "top_adsp", + "clk26m"; + }; + }; + +...