From patchwork Mon Jun 23 07:29:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Patchwork-Id: 899321 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9C251DF97F; Mon, 23 Jun 2025 07:32:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750663976; cv=none; b=vCZstQRJWp7wHEAgMjA626cnA75sBsOFveKAd9JCK3R2dfv2vTni1KEdkKoz+z0oxdwfFDSMGzO/GEw7I94L6IN83zKCDchiK1uUI7QXWp/xuSHT1nggqSK0h+H3JDLD88iS9j/dKW2B5DAbjvUzeZ/3io5OqkAPhgS0yrrTWzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750663976; c=relaxed/simple; bh=4lgeUcntkB8hGROx3TWd47HBW0Gu/RzofzkzRiKszu4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gdYrzs1BQjAeTAylNT9GlXUuF3d+VZ+MKmfWDGt2lxHy9FEUUccutz+HQMZ7d7GZVn+EixOJEpajXIqwIwTsSwPEiDydHBJki1hzxpXXFcyDTJqAX0djcv160POB0JISGcLh5e46tFUyYouIlg+kQLEAwrvkO4V2UVmXbMDd/Iw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=nIY1dq27; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="nIY1dq27" Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 55N6SOe6007060; Mon, 23 Jun 2025 09:32:41 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= Cp2gFOEZRolrC1cu3ilAyN1wQaeSGonjrUSYtHJ5W+g=; b=nIY1dq27k1s0HVdy 9gerPjYPN0Wg8jHlXS69o4x3YId8u/KilzSWczKm7NIjafYITro/qiD8r4uLGk3u pNj6iDcqKstQrAtUmsMKHNQkYrIY1mG9kpSQ80MJvxee5vY/D5Wqz8nWQu+WuFAB h7X+oiHSvKFq/mrE0j0lyQNv2p7u18qFI7cihHLtqUcWqtWEQT/b85FwnoM5+bpg NcUf10YbzgzYPPoLs2poKEWRBmly2mOJQ7fccfu2yafMTv3pR22ZZkTmZiq3Mq7z wLQHmxcyOYWhng5N3CyjvzwoLgNEeE2ZslHMoQKyexzjJ6mwRIiiB54SgTtxH6NE 8CBcJA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 47dm336ewj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 23 Jun 2025 09:32:41 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 86B144004F; Mon, 23 Jun 2025 09:31:34 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B4AC5B54303; Mon, 23 Jun 2025 09:29:44 +0200 (CEST) Received: from localhost (10.252.18.29) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 23 Jun 2025 09:29:44 +0200 From: =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= Date: Mon, 23 Jun 2025 09:29:14 +0200 Subject: [PATCH v6 4/8] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp13 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250623-hdp-upstream-v6-4-387536f08398@foss.st.com> References: <20250623-hdp-upstream-v6-0-387536f08398@foss.st.com> In-Reply-To: <20250623-hdp-upstream-v6-0-387536f08398@foss.st.com> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski , Antonio Borneo CC: , , , , , =?utf-8?q?Cl=C3=A9ment_Le_Goffic?= X-Mailer: b4 0.15-dev-c25d1 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-23_02,2025-06-20_01,2025-03-28_01 Add the hdp devicetree node for stm32mp13 SoC family. Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic --- arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 492bcf586361..7519ffa0dba8 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -954,6 +954,13 @@ dts: thermal@50028000 { status = "disabled"; }; + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp131-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>;