From patchwork Mon Feb 27 18:07:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 657356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73017C7EE23 for ; Mon, 27 Feb 2023 18:08:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230375AbjB0SI0 (ORCPT ); Mon, 27 Feb 2023 13:08:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230362AbjB0SIX (ORCPT ); Mon, 27 Feb 2023 13:08:23 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D735C162; Mon, 27 Feb 2023 10:08:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1677521287; x=1709057287; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uGfudpPPBewHcSdcBwT5jvm880EuRGAkt0xWNtVELqo=; b=uuYrWn0UppalZyxTc5eRcHt7Df3VHpF1N1dz7GskoKTutqCONNEWdpy+ AdO+3vXEN9n4w73pQYLeqSAYmyPs3bugxO25ZK9IVzFxJeZHKpWVEuV7r cKeUAxa3OXIkA/4qoLRBrfDNXa2COZ/RYHGqThTNWpv48SavJzsS6ejRZ LzHxx2TEkLaCg7bfCqny3U1GTG1ZP6xyDW6FGND5l7K1F7fuGioOgcbi5 vB58cXclgDPAKnveJ1VviFBEngCgXlz+6s/jlpsbi9rnjkhWUyfLLHpS0 7sCaTThs4QRHOq/RrM7ISYBT8cNJ2UPS1qt3dOiKUDElwWk9+rI1seTVF Q==; X-IronPort-AV: E=Sophos;i="5.98,219,1673938800"; d="scan'208";a="202436835" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 27 Feb 2023 11:07:27 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Mon, 27 Feb 2023 11:07:20 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Mon, 27 Feb 2023 11:07:20 -0700 From: To: , , , , , , CC: , , , , Ryan Wanner Subject: [PATCH v3 2/2] dt-bindings:pinctrl:at91:Adding macros for sama7g5 Date: Mon, 27 Feb 2023 11:07:28 -0700 Message-ID: <936fd3060662becd5485e32d5947286fcf0a3502.1677520830.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Ryan Wanner Adding macros for sama7g drive strength. Signed-off-by: Ryan Wanner --- changes since v1: - Fix ABI break. - Add explanation for drive strength macros. changes since v2: -Fix subject prefix to match subsystem. -Add more in-depth discription of sama7g5 define values. -Fix formatting issues. include/dt-bindings/pinctrl/at91.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h index e8e117306b1b..a02bee76b1fb 100644 --- a/include/dt-bindings/pinctrl/at91.h +++ b/include/dt-bindings/pinctrl/at91.h @@ -42,8 +42,21 @@ #define AT91_PERIPH_C 3 #define AT91_PERIPH_D 4 -#define ATMEL_PIO_DRVSTR_LO 1 +/*These macros are for all other at91 pinctrl drivers*/ +#define ATMEL_PIO_DRVSTR_LO 0 +#define ATMEL_PIO_DRVSTR_LO_1 1 #define ATMEL_PIO_DRVSTR_ME 2 #define ATMEL_PIO_DRVSTR_HI 3 +/* These macros are for the sama7g5 pinctrl driver + * Low D is low drive for GPIO mode or any non high-speed peripheral else Type D output impedance + * Hi A is high drive for GPIO mode or any non high-speed peripheral else Type A output impedance + * Low C is low drive for GPIO mode or any non high-speed peripheral else Type C output impedance + * Low B is low drive for GPIO mode or any non high-speed peripheral else Type B output impedance +*/ +#define ATMEL_PIO_DRVSTR_LO_D 0 +#define ATMEL_PIO_DRVSTR_HI_A 1 +#define ATMEL_PIO_DRVSTR_LO_C 2 +#define ATMEL_PIO_DRVSTR_LO_B 3 + #endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */