From patchwork Wed Apr 13 17:24:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 561307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47730C35280 for ; Wed, 13 Apr 2022 17:24:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237332AbiDMR1J (ORCPT ); Wed, 13 Apr 2022 13:27:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237337AbiDMR05 (ORCPT ); Wed, 13 Apr 2022 13:26:57 -0400 Received: from albert.telenet-ops.be (albert.telenet-ops.be [IPv6:2a02:1800:110:4::f00:1a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7780E9F for ; Wed, 13 Apr 2022 10:24:20 -0700 (PDT) Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed40:c9b8:20d3:ee2b:1cda]) by albert.telenet-ops.be with bizsmtp id JHQH270092t8Arn06HQHfd; Wed, 13 Apr 2022 19:24:17 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1negj3-000TtT-3O; Wed, 13 Apr 2022 19:24:17 +0200 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1negj1-00DfbZ-Rm; Wed, 13 Apr 2022 19:24:15 +0200 From: Geert Uytterhoeven To: Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 50/50] pinctrl: renesas: checker: Add reserved field checks Date: Wed, 13 Apr 2022 19:24:12 +0200 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add checks for discovering registers with reserved fields that could benefit from being described using variable-width reserved field shorthands, reducing kernel size. Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/core.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 356325df9c18f2ea..340835551466235f 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -878,7 +878,7 @@ static const struct sh_pfc_pin __init *sh_pfc_find_pin( static void __init sh_pfc_check_cfg_reg(const char *drvname, const struct pinmux_cfg_reg *cfg_reg) { - unsigned int i, n, rw; + unsigned int i, n, rw, r; int fw; sh_pfc_check_reg(drvname, cfg_reg->reg, @@ -887,6 +887,15 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname, if (cfg_reg->field_width) { fw = cfg_reg->field_width; n = (cfg_reg->reg_width / fw) << fw; + for (i = 0, r = 0; i < n; i += 1 << fw) { + if (is0s(&cfg_reg->enum_ids[i], 1 << fw)) + r++; + } + + if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw) + sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n", + cfg_reg->reg); + /* Skip field checks (done at build time) */ goto check_enum_ids; }