From patchwork Thu Nov 21 13:01:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jyothi Kumar Seerapu X-Patchwork-Id: 844984 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B70191C6F76; Thu, 21 Nov 2024 13:02:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732194122; cv=none; b=fO1gAUBBt6gTWadgEs0iG2tIefeSuL39OuBbXA5/ynyrGIUB+l8MKqZqFZBlZyI9Eu9WTWaVOWhdYfAhtmXTxoxaNvQSKPhzm2YVHRh0DxJHZbt4tIPzGGLP5rSmWm0RUt8X8jxJ0yM5SIuN9PI39b9fhlxDJMqSqantipiGAPc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732194122; c=relaxed/simple; bh=H3kgiiRnUmZjLZ5rnsuw4jsYjUXA/LW8BJg5QnP4vuk=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=AgISgo7dMOVui9sse7JhPQKwcEOArH14oxA3OA0skCa3/Jmk2QLB9rRRCnkaCwXIJWcVrPK6A5vamSbAm2HhsVABTktU6ATpGr2w8uwZ0/2PDqb1tIdSRMr3srSTWJ3zmxZ2zlAAnYkpUI2ER2ufIlIfy/t29jeYcrYR6prjcKw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=EfbSU6JY; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="EfbSU6JY" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AL8wPAd003970; Thu, 21 Nov 2024 13:01:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-type:date:from:message-id:mime-version:subject:to; s= qcppdkim1; bh=+Cw9AmePfDfuyTVESkI3jt2/6IYMbJ83JCwVBkae/fg=; b=Ef bSU6JYIVKWJhDE3ftBUPPuK9VqkegomivNPTn0PeDpWkpa7LXck90xhQWRm7rXHV vEm8//7Uc8VNpfOJmJKZ0DmgG4+1Wu/+lHiQ6OpH0jKSFvogynqed/MqEJgdvC2J ZFvOuZC5Eo34pZSi4OTFVOyyjG2NOvq0k4sY12i8B47EIxGYr5mJrjxJsqIquDdM 7qkhZ8A3Jrbi293V+flnH/Xjl1lIxyXco2kebGqYpPagxkqyydRBB2KodpKcNZ0c kCFVwnCqB4EnQYZ5Gt8pOVE1igbNizM2RuWhLWG+/qHRoxFL67cn+BiwDBGH1JKO A6L52mGUa7MyIPN0QwTA== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 431ce3c3e5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 13:01:53 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ALD1qll005863 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Nov 2024 13:01:52 GMT Received: from hu-jseerapu-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 21 Nov 2024 05:01:48 -0800 From: Jyothi Kumar Seerapu To: Vinod Koul , Andi Shyti , "Sumit Semwal" , =?utf-8?q?Christian_K=C3=B6nig?= CC: , , , , , , , , Subject: [PATCH v3 0/3] Add Block event interrupt support for I2C protocol Date: Thu, 21 Nov 2024 18:31:31 +0530 Message-ID: <20241121130134.29408-1-quic_jseerapu@quicinc.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: RAc_oPQxbIbgKKAjLAEjeoLSYuUSfWwo X-Proofpoint-ORIG-GUID: RAc_oPQxbIbgKKAjLAEjeoLSYuUSfWwo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 spamscore=0 mlxlogscore=999 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411210102 The I2C driver gets an interrupt upon transfer completion. When handling multiple messages in a single transfer, this results in N interrupts for N messages, leading to significant software interrupt latency. To mitigate this latency, utilize Block Event Interrupt (BEI) mechanism. Enabling BEI instructs the hardware to prevent interrupt generation and BEI is disabled when an interrupt is necessary. Large I2C transfer can be divided into chunks of 8 messages internally. Interrupts are not expected for the first 7 message completions, only the last message triggers an interrupt, indicating the completion of 8 messages. This BEI mechanism enhances overall transfer efficiency. This optimization reduces transfer time from 168 ms to 48 ms for a series of 200 I2C write messages in a single transfer, with a clock frequency support of 100 kHz. BEI optimizations are currently implemented for I2C write transfers only, as there is no use case for multiple I2C read messages in a single transfer at this time. v2 -> v3: - Updated commit description - In I2C GENI driver, for i2c_gpi_cb_result moved the logic of "!is_tx_multi_xfer" to else part. - MIN_NUM_OF_MSGS_MULTI_DESC changed from 4 to 2 - Changes of I2C GENI driver to depend on the GPI driver moved to patch3. - Renamed gpi_multi_desc_process to gpi_multi_xfer_timeout_handler - Added description for newly added changes in "qcom-gpi-dma.h" file. v1 -> v2: - DT changes are reverted for adding dma channel size as a new arg of dma-cells property. - DT binding change reveted for dma channel size as a new arg of dma-cells property. - In GPI driver, reverted the changes to parse the channel TRE size from device tree. - Made the changes in QCOM I2C geni driver to support the BEI functionality with the existing TRE size of 64. - Made changes in QCOM I2C geni driver as per the review comments. - Fixed Kernel test robot reported compiltion issues. Jyothi Kumar Seerapu (3): dmaengine: qcom: gpi: Add GPI Block event interrupt support i2c: i2c-qcom-geni: Add Block event interrupt support i2c: i2c-qcom-geni: Update compile dependenices for i2c qcom geni drivers/dma/qcom/gpi.c | 48 +++++++ drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-qcom-geni.c | 203 +++++++++++++++++++++++++---- include/linux/dma/qcom-gpi-dma.h | 76 +++++++++++ 4 files changed, 303 insertions(+), 25 deletions(-) base-commit: 55bcd2e0d04c1171d382badef1def1fd04ef66c5