From patchwork Tue Jul 14 07:36:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 51091 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f199.google.com (mail-wi0-f199.google.com [209.85.212.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 86369202B9 for ; Tue, 14 Jul 2015 07:40:05 +0000 (UTC) Received: by wizo10 with SMTP id o10sf2429401wiz.0 for ; Tue, 14 Jul 2015 00:40:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=inZypYmIR2H6KcsKXpMTFLTOghPYELfFbpxzEj1nrqU=; b=X7XhvRCP8l2PkbXfwhCxGsiy3YJdYB+fVpzl1zjF0Ytr3VYXCcJk7k9/ns1G3Aa1c0 y/m0AqLy/eZgvAmlMI/laBcdrXqzzOQpXyM7N1g1kxH8M34MDfVCqGbai39y3EFIPMEy Ol1AXzyUd+R53MqFO9fuSCvKJnEamm4H5zXwoObt/IwK8h8WxE0AQVA3PqHv8NKt0OYD rzgtXQAbN8pM9q9Ed9VpcSV4ejynQYUVUL9h8vzLitMtGGGru9wJUiieSHWieR8x4Q11 eLMqFB4X186SDbopIgzz2V0M5vQvHr2i7eFjTZlgOI05OQSXdkyfO6K1khJvHwSmaua1 ehlg== X-Gm-Message-State: ALoCoQlR1y+1LhP9T+twrXqzpjGPvRKqrgcjpdveCWH0+3weDR0eShA3nxaWVNNxZh6TuRI4db+u X-Received: by 10.181.13.202 with SMTP id fa10mr791168wid.4.1436859604877; Tue, 14 Jul 2015 00:40:04 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.225 with SMTP id v1ls7715lav.71.gmail; Tue, 14 Jul 2015 00:40:04 -0700 (PDT) X-Received: by 10.112.25.69 with SMTP id a5mr35761943lbg.16.1436859604712; Tue, 14 Jul 2015 00:40:04 -0700 (PDT) Received: from mail-lb0-f181.google.com (mail-lb0-f181.google.com. [209.85.217.181]) by mx.google.com with ESMTPS id ay7si161755lbc.60.2015.07.14.00.40.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Jul 2015 00:40:04 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) client-ip=209.85.217.181; Received: by lbbzr7 with SMTP id zr7so1106480lbb.1 for ; Tue, 14 Jul 2015 00:40:04 -0700 (PDT) X-Received: by 10.152.26.163 with SMTP id m3mr36274835lag.86.1436859604591; Tue, 14 Jul 2015 00:40:04 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp2195275lbb; Tue, 14 Jul 2015 00:40:03 -0700 (PDT) X-Received: by 10.70.53.99 with SMTP id a3mr77965255pdp.169.1436859594529; Tue, 14 Jul 2015 00:39:54 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id iw6si274272pbd.183.2015.07.14.00.39.53; Tue, 14 Jul 2015 00:39:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-i2c-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753376AbbGNHjr (ORCPT + 1 other); Tue, 14 Jul 2015 03:39:47 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:34310 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753313AbbGNHjp (ORCPT ); Tue, 14 Jul 2015 03:39:45 -0400 Received: by pacan13 with SMTP id an13so1356520pac.1 for ; Tue, 14 Jul 2015 00:39:44 -0700 (PDT) X-Received: by 10.70.40.164 with SMTP id y4mr77995298pdk.25.1436859584770; Tue, 14 Jul 2015 00:39:44 -0700 (PDT) Received: from localhost.localdomain ([202.62.77.106]) by smtp.gmail.com with ESMTPSA id pe3sm275937pdb.55.2015.07.14.00.39.41 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Jul 2015 00:39:43 -0700 (PDT) From: Vaibhav Hiremath To: linux-i2c@vger.kernel.org Cc: wsa@the-dreams.de, robh+dt@kernel.org, robert.jarzmik@free.fr, yizhang@marvell.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Vaibhav Hiremath , "Jett.Zhou" Subject: [PATCH-v4 09/11] i2c: pxa: Add support for pxa910/988 & new configuration features Date: Tue, 14 Jul 2015 13:06:48 +0530 Message-Id: <1436859410-28878-10-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1436859410-28878-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1436859410-28878-1-git-send-email-vaibhav.hiremath@linaro.org> Sender: linux-i2c-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-i2c@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vaibhav.hiremath@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , TWSI_ILCR & TWSI_IWCR registers are used to adjust clock rate of standard & fast mode in pxa910/988; so this patch adds these two new entries to "struct pxa_reg_layout" and "struct pxa_i2c". As discussed in the previous patch-series, the idea here is to add standard DT properties for ilcr and iwcr configuration fields. In case of Master ilcr is used for low/high time and in case of slave mode of operation iwcr is used for setup/hold time. Signed-off-by: Jett.Zhou Signed-off-by: Yi Zhang Signed-off-by: Vaibhav Hiremath --- drivers/i2c/busses/i2c-pxa.c | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index abf04f2..8d76197 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -46,12 +46,15 @@ struct pxa_reg_layout { u32 icr; u32 isr; u32 isar; + u32 ilcr; + u32 iwcr; }; enum pxa_i2c_types { REGS_PXA2XX, REGS_PXA3XX, REGS_CE4100, + REGS_PXA910, }; /* @@ -79,12 +82,22 @@ static struct pxa_reg_layout pxa_reg_layout[] = { .isr = 0x04, /* no isar register */ }, + [REGS_PXA910] = { + .ibmr = 0x00, + .idbr = 0x08, + .icr = 0x10, + .isr = 0x18, + .isar = 0x20, + .ilcr = 0x28, + .iwcr = 0x30, + }, }; static const struct platform_device_id i2c_pxa_id_table[] = { { "pxa2xx-i2c", REGS_PXA2XX }, { "pxa3xx-pwri2c", REGS_PXA3XX }, { "ce4100-i2c", REGS_CE4100 }, + { "pxa910-i2c", REGS_PXA910 }, { }, }; MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); @@ -124,6 +137,24 @@ MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); #define ISR_SAD (1 << 9) /* slave address detected */ #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ +/* bit field shift & mask */ +#define ILCR_SLV_SHIFT 0 +#define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT) +#define ILCR_FLV_SHIFT 9 +#define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT) +#define ILCR_HLVL_SHIFT 18 +#define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT) +#define ILCR_HLVH_SHIFT 27 +#define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT) + +#define IWCR_CNT_SHIFT 0 +#define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT) +#define IWCR_HS_CNT1_SHIFT 5 +#define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT) +#define IWCR_HS_CNT2_SHIFT 10 +#define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT) + + struct pxa_i2c { spinlock_t lock; wait_queue_head_t wait; @@ -150,6 +181,8 @@ struct pxa_i2c { void __iomem *reg_icr; void __iomem *reg_isr; void __iomem *reg_isar; + void __iomem *reg_ilcr; + void __iomem *reg_iwcr; unsigned long iobase; unsigned long iosize; @@ -169,6 +202,8 @@ struct pxa_i2c { #define _ICR(i2c) ((i2c)->reg_icr) #define _ISR(i2c) ((i2c)->reg_isr) #define _ISAR(i2c) ((i2c)->reg_isar) +#define _ILCR(i2c) ((i2c)->reg_ilcr) +#define _IWCR(i2c) ((i2c)->reg_iwcr) /* * I2C Slave mode address @@ -1135,7 +1170,7 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = { static const struct of_device_id i2c_pxa_dt_ids[] = { { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX }, { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX }, - { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX }, + { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 }, {} }; MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); @@ -1243,6 +1278,11 @@ static int i2c_pxa_probe(struct platform_device *dev) if (i2c_type != REGS_CE4100) i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; + if (i2c_type == REGS_PXA910) { + i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr; + i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr; + } + i2c->iobase = res->start; i2c->iosize = resource_size(res);