From patchwork Wed Jun 10 06:02:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 207524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61B86C433E1 for ; Wed, 10 Jun 2020 06:03:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D40A2081A for ; Wed, 10 Jun 2020 06:03:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="ei59UQXi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726305AbgFJGC7 (ORCPT ); Wed, 10 Jun 2020 02:02:59 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11231 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726268AbgFJGCu (ORCPT ); Wed, 10 Jun 2020 02:02:50 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:18 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:50 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:50 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:49 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:49 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 09 Jun 2020 23:02:49 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 10/18] dt-bindings: tegra: Document VI and CSI port nodes Date: Tue, 9 Jun 2020 23:02:32 -0700 Message-ID: <1591768960-31648-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768878; bh=wPUjcK5pjatayPbHQg+cG5OdMe7PMrZuDRJsqwl5MoU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ei59UQXi7yEOg3WW32Mp1G+liqrIbq6KgKYXkk5nfw4KS4XF6G1yTXTM4NS+8WpFB 74gYnQSUQz5zn6ViJqqtSIM4vz2NRmAYhgfO+U1QT4Uk2IcGrVB8/ajaCkbm8C3iVj bUWH2UR0uUDnV3vvyjurqDumaWcl6tCQ5uAxKeH4EvESVuDWISRSDc3Ysn8xgh+ha4 nVGS/9bnwsxhQ3HLVmgoGyjACSF6pWPzN7tnqR23rr3pAzKVpxylFeR78yZnHwFq4w OhV1OyaWPXqNHwyFlikaNPLlwrGQNcAUgbP0Y5uRp1HVP4HK5iw9RcpgksXCpW//UT AJJlQOjq0R06g== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org This patch documents Tegra VI and CSI port and endpoint nodes along with the other required properties. Signed-off-by: Sowjanya Komatineni --- .../display/tegra/nvidia,tegra20-host1x.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 4731921..f70a838 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -65,6 +65,48 @@ of the following host1x client modules: - power-domains: Must include sor powergate node as csicil is in SOR partition. + Optional properties for csi node: + + - channel nodes: Max upto 6 channels/streams are supported with each CSI + brick can as either x4 or x2 based on hw connectivity to sensor. + + Required properties: + - reg: channel/stream index + - nvidia,mipi-calibrate: Should contain a phandle and a specifier + specifying which pads are used by this CSI port and need to be + calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt. + + - port: CSI port node and its endpoint nodes as per device graph + bindings defined in Documentation/devicetree/bindings/graph.txt. + Required properties: + - reg: csi port index based on hw csi lanes connectivity to the + sensor. + - bus-width: number of lanes used by this port. Supported lanes + are 1/2/4. + - endpoint@0: sink node + Required properties: + - reg: endpoint id. This is used to retrieve pad for creating + media link + - remote-endpoint: phandle to sensor endpoint + - endpoint@1: source node + - reg: endpoint id. This is used to retrieve pad for creating + media link + - remote-endpoint: phandle to vi port endpoint + + Optional properties for vi node: + - ports: Video port nodes and endpoint nodes as per device graph bindings + defined in Documentation/devicetree/bindings/graph.txt + Max 6 ports are supported and each port should have one endpoint node. + + Required properties: + - port: VI port node and its sink endpoint node + Required properties: + - reg: should match port index + - endpoint@0: sink node + Required properties: + - reg: endpoint id must be 0 + - remote-endpoint: phandle to CSI endpoint node. + - epp: encoder pre-processor Required properties: @@ -340,6 +382,22 @@ Example: ranges = <0x0 0x0 0x54080000 0x2000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + imx219_vi_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&imx219_csi_out0>; + }; + }; + }; + csi@838 { compatible = "nvidia,tegra210-csi"; reg = <0x838 0x1300>; @@ -362,6 +420,35 @@ Example: <&tegra_car TEGRA210_CLK_CSI_TPG>; clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; power-domains = <&pd_sor>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + nvidia,mipi-calibrate = <&mipi 0x001>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bus-width = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + imx219_csi_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&imx219_out0>; + }; + + imx219_csi_out0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx219_vi_in0>; + }; + }; + }; }; };