From patchwork Wed Jun 10 06:02:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 207518 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45C71C433E2 for ; Wed, 10 Jun 2020 06:04:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1E72920801 for ; Wed, 10 Jun 2020 06:04:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="qfnckt+M" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726524AbgFJGE2 (ORCPT ); Wed, 10 Jun 2020 02:04:28 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:11212 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726186AbgFJGCr (ORCPT ); Wed, 10 Jun 2020 02:02:47 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 23:01:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 23:02:46 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 23:02:46 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 10 Jun 2020 06:02:46 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 10 Jun 2020 06:02:46 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.70]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 09 Jun 2020 23:02:45 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 04/18] i2c: tegra: Fix the error path in tegra_i2c_runtime_resume Date: Tue, 9 Jun 2020 23:02:26 -0700 Message-ID: <1591768960-31648-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> References: <1591768960-31648-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591768875; bh=FE3zccXsSJw4dQg1KvzPkaznm8tF4D5l77Bo/LLBkaM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qfnckt+MTSZJWTCS16Faw36qp6V4mxwiqEgki2rm3rbSG7DWgXxUyNTa3NxsA5cba nL44D04iaCA9aoZuHtZK411MM8affCmuMTh6zewkeNFu5BxqkFVSo25rLy1Tv6471g ZFIcKA/nexHymQuOA8t+0YnzzC7+l4mlSWlsdiXWWSBWMQa5AotXDOrcPrQik88It0 ktkE5PdpkesyxBBJ/Oits55fH7vcNBDOlF3BoMaL/aEK/OBt4YCzJKinScJilVkK0d 76Zc5Jp++lqeh52QQ1TYRzTJaTuZW7Ne35Rel815zpWVQ+/GozzX42sq5d1RCOACam xU+5Nv8brGFHA== Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org tegra_i2c_runtime_resume does not disable prior enabled clocks properly. This patch fixes it. Signed-off-by: Sowjanya Komatineni --- drivers/i2c/busses/i2c-tegra.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 3be1018..dba38a5 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -668,7 +668,7 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) ret = clk_enable(i2c_dev->slow_clk); if (ret < 0) { dev_err(dev, "failed to enable slow clock: %d\n", ret); - return ret; + goto disable_fast_clk; } } @@ -676,11 +676,18 @@ static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) if (ret < 0) { dev_err(i2c_dev->dev, "Enabling div clk failed, err %d\n", ret); - clk_disable(i2c_dev->fast_clk); - return ret; + goto disable_slow_clk; } return 0; + +disable_slow_clk: + if (i2c_dev->slow_clk) + clk_disable(i2c_dev->slow_clk); +disable_fast_clk: + if (!i2c_dev->hw->has_single_clk_source) + clk_disable(i2c_dev->fast_clk); + return ret; } static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)