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Mon, 24 Jan 2022 03:18:51 -0800 From: Akhil R To: , , , , , , , , , CC: Subject: [PATCH v3 3/4] dt-bindings: Add headers for Tegra234 PWM Date: Mon, 24 Jan 2022 16:48:16 +0530 Message-ID: <1643023097-5221-4-git-send-email-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com> References: <1643023097-5221-1-git-send-email-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f1f05855-f5d2-4958-9470-08d9df2b4f75 X-MS-TrafficTypeDiagnostic: DM4PR12MB5341:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1186; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GloJBXbCf6/8MkEMloNt5FkRJsSl+8JX8WMeNCwcJMp+dWVSRel0P6RwVf8o1SeMGFnOTBUWIaFEy6ewkwXFV9vA0yaNA+U6sHZre7Zcj2pOjB928tiLRUuF7jviOcBb7QR+TRPiAumb8qtU+veK8iGklBVgVkPl/nJYfaBP+B2f2Q3vaPBzI1+O+xwv/U2UNfJiPep7DcXXed+Tvcut+cOoR8eA6XwwJbk1VsRDqetpwZ76TsOv2sJNKAewWcoYIYT3ZwxVWQJoHf6NzXw2uSInOMJBByowW6TOO4frExNj+rWbmOykEjvSbUjTYLa5YZITW1+k497wyLEJ5fQqOXt6tp7HeNSIxiW1gSIuK4gu8ng1noQpM5XqqTWFF4E2sNwx0waEezYcissFpQc/VtXGhblJNN5ZGcb/AkBf0VKrw0mOHTOnkTvfUVNPFxGk5FZZJ/hbeU+IHNio1VCIN5s57pK87clTmDpv/h9mBccXAi4yrxveiXhhfkM6wBEOKZSzleIEC35V9NC+sAaG9p5FH6Fvzex0zvJ6/CTZuHdGbzlP40e/5MGAH2NaOYVcIlG+RmBgV71xUZORZSHYsgFyYpZRXvFtZ7wKVqDxu0uyvggRPWDJrAjWRoExG9vppipJ/G3yz8+lc+MHR8F9TAMLXU48qAXB/urSmBavLRdeps9kbaGTlPPvvOPq8kRGezOtNVnYu4T6nSBOLifcxxwKNm2Q9XkIHHkhNfff8ldli9uo6fSLyaiSONnQmvla99F9yrj6dsAzxQ9XPYqavyf13gRtjByKWK62XUebt+5Nh22FZON3PdR6ZHL0R9ewmJqvV5gqAQYdqGaEuoK/yROSdjpzrCGWDvqygKU+D3g= X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(36840700001)(46966006)(47076005)(508600001)(86362001)(36756003)(356005)(83380400001)(4326008)(426003)(5660300002)(107886003)(26005)(921005)(186003)(316002)(36860700001)(70206006)(81166007)(82310400004)(2616005)(6666004)(110136005)(8936002)(2906002)(336012)(8676002)(70586007)(7696005)(40460700003)(36900700001)(2101003)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jan 2022 11:18:55.7610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1f05855-f5d2-4958-9470-08d9df2b4f75 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5341 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add dt-bindings header files for PWM of Tegra234 Signed-off-by: Akhil R --- include/dt-bindings/clock/tegra234-clock.h | 16 ++++++++++++++++ include/dt-bindings/reset/tegra234-reset.h | 8 ++++++++ 2 files changed, 24 insertions(+) diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index dc524e6..2529e7e 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -38,6 +38,22 @@ #define TEGRA234_CLK_I2C9 55U /** @brief PLLP clk output */ #define TEGRA234_CLK_PLLP_OUT0 102U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA234_CLK_PWM1 105U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA234_CLK_PWM2 106U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA234_CLK_PWM3 107U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA234_CLK_PWM4 108U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA234_CLK_PWM5 109U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA234_CLK_PWM6 110U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA234_CLK_PWM7 111U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA234_CLK_PWM8 112U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ #define TEGRA234_CLK_SDMMC4 123U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 2963259..ba390b8 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -18,6 +18,14 @@ #define TEGRA234_RESET_I2C7 33U #define TEGRA234_RESET_I2C8 34U #define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_PWM1 68U +#define TEGRA234_RESET_PWM2 69U +#define TEGRA234_RESET_PWM3 70U +#define TEGRA234_RESET_PWM4 71U +#define TEGRA234_RESET_PWM5 72U +#define TEGRA234_RESET_PWM6 73U +#define TEGRA234_RESET_PWM7 74U +#define TEGRA234_RESET_PWM8 75U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U