@@ -419,8 +419,8 @@ static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
{
struct dma_chan *chan;
- u32 *dma_buf;
dma_addr_t dma_phys;
+ u32 *dma_buf;
int err;
if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
@@ -523,11 +523,11 @@ static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
{
- u32 val;
- int rx_fifo_avail;
- u8 *buf = i2c_dev->msg_buf;
size_t buf_remaining = i2c_dev->msg_buf_remaining;
+ u8 *buf = i2c_dev->msg_buf;
int words_to_transfer;
+ int rx_fifo_avail;
+ u32 val;
/*
* Catch overflow due to message fully sent
@@ -584,11 +584,11 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
{
- u32 val;
- int tx_fifo_avail;
- u8 *buf = i2c_dev->msg_buf;
size_t buf_remaining = i2c_dev->msg_buf_remaining;
+ u8 *buf = i2c_dev->msg_buf;
int words_to_transfer;
+ int tx_fifo_avail;
+ u32 val;
if (i2c_dev->hw->has_mst_fifo) {
val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
@@ -794,11 +794,8 @@ static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit)
{
- u32 val;
+ u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh;
int err;
- u32 clk_divisor, clk_multiplier;
- u32 tsu_thd;
- u8 tlow, thigh;
err = reset_control_reset(i2c_dev->rst);
if (WARN_ON_ONCE(err))
@@ -906,9 +903,9 @@ static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
{
- u32 status;
const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
struct tegra_i2c_dev *i2c_dev = dev_id;
+ u32 status;
status = i2c_readl(i2c_dev, I2C_INT_STATUS);
@@ -1012,12 +1009,11 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
size_t len)
{
- u32 val, reg;
- u8 dma_burst;
struct dma_slave_config slv_config = {0};
+ unsigned long reg_offset;
+ u32 val, reg, dma_burst;
struct dma_chan *chan;
int ret;
- unsigned long reg_offset;
if (i2c_dev->hw->has_mst_fifo)
reg = I2C_MST_FIFO_CONTROL;
@@ -1142,9 +1138,9 @@ tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev,
static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
{
struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
- int err;
unsigned long time_left;
u32 reg;
+ int err;
reinit_completion(&i2c_dev->msg_complete);
reg = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
@@ -1180,14 +1176,12 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
struct i2c_msg *msg,
enum msg_end_type end_state)
{
- u32 packet_header;
- u32 int_mask;
- unsigned long time_left;
- size_t xfer_size;
+ unsigned long time_left, xfer_time = 100;
+ u32 packet_header, int_mask;
u32 *buffer = NULL;
- int err = 0;
+ size_t xfer_size;
bool dma;
- u16 xfer_time = 100;
+ int err;
err = tegra_i2c_flush_fifos(i2c_dev);
if (err)
@@ -1381,8 +1375,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
int num)
{
struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
- int i;
- int ret;
+ int i, ret;
ret = pm_runtime_get_sync(i2c_dev->dev);
if (ret < 0) {
@@ -1437,8 +1430,8 @@ static u32 tegra_i2c_func(struct i2c_adapter *adap)
static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
{
struct device_node *np = i2c_dev->dev->of_node;
- int ret;
bool multi_mode;
+ int ret;
ret = of_property_read_u32(np, "clock-frequency",
&i2c_dev->bus_clk_rate);
@@ -1664,14 +1657,12 @@ MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
static int tegra_i2c_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ struct clk *div_clk, *fast_clk;
struct tegra_i2c_dev *i2c_dev;
+ phys_addr_t base_phys;
struct resource *res;
- struct clk *div_clk;
- struct clk *fast_clk;
void __iomem *base;
- phys_addr_t base_phys;
- int irq;
- int ret;
+ int irq, ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base_phys = res->start;