From patchwork Sun Jun 5 13:32:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 578902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7523BC433EF for ; Sun, 5 Jun 2022 13:33:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244854AbiFENdW (ORCPT ); Sun, 5 Jun 2022 09:33:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241332AbiFENdV (ORCPT ); Sun, 5 Jun 2022 09:33:21 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE98938D8D for ; Sun, 5 Jun 2022 06:33:19 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id m32-20020a05600c3b2000b0039756bb41f2so6601908wms.3 for ; Sun, 05 Jun 2022 06:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iD0AT9Ulc1i16U7giR4n88maA1Cd/1tBAzCeefFKFTY=; b=ILnwRkHVIcM9WPFdbjX0m54y//OEZHvWFBEO5lTy+DYw3ARheHtNZ2jKwQIcWJP1bw SSpxhIMnPMWIck/KeG0x3/JHuGPfZRqBDkBkMDiwMgWVsnVfWeUeN4OHJnu4PWABD422 MhP0I7MNeQgfFtQ6NamRDRMb7hRrFQVkrizly2s7TYYpFPBkmCmwPlSAaUtLT/3cDBWB TaLnbLz/325+osIuWILxSyB8V5CM0A48RrOHE6DwXYRA1MKYjNPLq1n3zExaHujZydWA BowYDDQkhKDTvauumfUdu8PGed5QENOWO780QH2I8BZaO+JKJGmlkLWAT3ZA6zTA2fc+ mHWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iD0AT9Ulc1i16U7giR4n88maA1Cd/1tBAzCeefFKFTY=; b=emlo3KAlAh3SJXnMHIdBjORpNggDP3tZnt2tbCpdA6TDU8KqL3YhQN2xlY98mGPG5k DxTHZhKzfSkgEhM8CP3jwERC0yeYvHHY4jVKQu4CoxXCIBNMztCB8IFd43DhIjbJouaj 9OM8Z90o1Qa3hojMVmXMyuF0iEjR5foWSyaVadYlxCBlix8FPlr7OlobOp5UpPuc7hRP E8MTq8LINkoi2Qkk/wvBObiGJqgVeza1ju0Bh7pWbTkeNjKD1TryBnvgKDFZy81EfRU7 zn2aaFrkyNMaMfNIhEW+e1Yylwo914dzqVGSQ8RCROyTDNfPorTOHQ1BFmh+8NLm69yv P/TQ== X-Gm-Message-State: AOAM532JJJbSmGjl4EOU2JuMboAIXIsPqtbbw0JsjkZeo8k+f0Rd4Exm vNKmZNK8HkUs+PGCBLjclT3t5A== X-Google-Smtp-Source: ABdhPJzy3arg2urk/arEHLc/LofFxNLx6PWCgGfxODw4J3E1atFORuRSw5c2jxJ1KoeetRxv07o/xw== X-Received: by 2002:a05:600c:378d:b0:39c:4950:aef8 with SMTP id o13-20020a05600c378d00b0039c4950aef8mr5251629wmr.96.1654435997986; Sun, 05 Jun 2022 06:33:17 -0700 (PDT) Received: from henark71.. ([51.37.234.167]) by smtp.gmail.com with ESMTPSA id n187-20020a1c27c4000000b0039c151298b7sm18217076wmn.10.2022.06.05.06.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jun 2022 06:33:17 -0700 (PDT) From: mail@conchuod.ie To: Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Support Opensource , Lee Jones , Ulf Hansson , Palmer Dabbelt , Paul Walmsley , Albert Ou , Steve Twiss Cc: Conor Dooley , linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-riscv@lists.infradead.org, Atul Khare Subject: [PATCH v1 2/6] dt-bindings: i2c: convert ocores binding to yaml Date: Sun, 5 Jun 2022 14:32:57 +0100 Message-Id: <20220605133300.376161-3-mail@conchuod.ie> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220605133300.376161-1-mail@conchuod.ie> References: <20220605133300.376161-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Conor Dooley Convert the open cores i2c controller binding from text to yaml. Signed-off-by: Conor Dooley --- .../devicetree/bindings/i2c/i2c-ocores.txt | 78 ----------- .../devicetree/bindings/i2c/i2c-ocores.yaml | 132 ++++++++++++++++++ 2 files changed, 132 insertions(+), 78 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-ocores.txt create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ocores.yaml diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt deleted file mode 100644 index a37c9455b244..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt +++ /dev/null @@ -1,78 +0,0 @@ -Device tree configuration for i2c-ocores - -Required properties: -- compatible : "opencores,i2c-ocores" - "aeroflexgaisler,i2cmst" - "sifive,fu540-c000-i2c", "sifive,i2c0" - For Opencore based I2C IP block reimplemented in - FU540-C000 SoC. - "sifive,fu740-c000-i2c", "sifive,i2c0" - For Opencore based I2C IP block reimplemented in - FU740-C000 SoC. - Please refer to sifive-blocks-ip-versioning.txt for - additional details. -- reg : bus address start and address range size of device -- clocks : handle to the controller clock; see the note below. - Mutually exclusive with opencores,ip-clock-frequency -- opencores,ip-clock-frequency: frequency of the controller clock in Hz; - see the note below. Mutually exclusive with clocks -- #address-cells : should be <1> -- #size-cells : should be <0> - -Optional properties: -- interrupts : interrupt number. -- clock-frequency : frequency of bus clock in Hz; see the note below. - Defaults to 100 KHz when the property is not specified -- reg-shift : device register offsets are shifted by this value -- reg-io-width : io register width in bytes (1, 2 or 4) -- regstep : deprecated, use reg-shift above - -Note -clock-frequency property is meant to control the bus frequency for i2c bus -drivers, but it was incorrectly used to specify i2c controller input clock -frequency. So the following rules are set to fix this situation: -- if clock-frequency is present and neither opencores,ip-clock-frequency nor - clocks are, then clock-frequency specifies i2c controller clock frequency. - This is to keep backwards compatibility with setups using old DTB. i2c bus - frequency is fixed at 100 KHz. -- if clocks is present it specifies i2c controller clock. clock-frequency - property specifies i2c bus frequency. -- if opencores,ip-clock-frequency is present it specifies i2c controller - clock frequency. clock-frequency property specifies i2c bus frequency. - -Examples: - - i2c0: ocores@a0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "opencores,i2c-ocores"; - reg = <0xa0000000 0x8>; - interrupts = <10>; - opencores,ip-clock-frequency = <20000000>; - - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ - - dummy@60 { - compatible = "dummy"; - reg = <0x60>; - }; - }; -or - i2c0: ocores@a0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "opencores,i2c-ocores"; - reg = <0xa0000000 0x8>; - interrupts = <10>; - clocks = <&osc>; - clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ - - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ - - dummy@60 { - compatible = "dummy"; - reg = <0x60>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.yaml b/Documentation/devicetree/bindings/i2c/i2c-ocores.yaml new file mode 100644 index 000000000000..1693ffffbe31 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-ocores.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-ocores.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores I2C controller + +maintainers: + - Peter Korsgaard + - Andrew Lunn + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC + - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC + - const: sifive,i2c0 + - const: opencores,i2c-ocores + - const: aeroflexgaisler,i2cmst + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clock-frequency: + description: | + Desired I2C bus clock frequency in Hz. As only Standard and Fast + modes are supported, possible values are 100000 and 400000. + Note: + clock-frequency property is meant to control the bus frequency for i2c bus + drivers, but it was incorrectly used to specify i2c controller input clock + frequency. So the following rules are set to fix this situation: + - if clock-frequency is present and neither opencores,ip-clock-frequency nor + clocks are, then clock-frequency specifies i2c controller clock frequency. + This is to keep backwards compatibility with setups using old DTB. i2c bus + frequency is fixed at 100 KHz. + - if clocks is present it specifies i2c controller clock. clock-frequency + property specifies i2c bus frequency. + - if opencores,ip-clock-frequency is present it specifies i2c controller + clock frequency. clock-frequency property specifies i2c bus frequency. + default: 100000 + + reg-io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + io register width in bytes + enum: [1, 2, 4] + + reg-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + device register offsets are shifted by this value + + regstep: + description: | + deprecated, use reg-shift above + deprecated: true + + opencores,ip-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Frequency of the controller clock in Hz. Mutually exclusive with clocks. + See the note above. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +oneOf: + - required: + - opencores,ip-clock-frequency + - required: + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@a0000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "opencores,i2c-ocores"; + reg = <0xa0000000 0x8>; + interrupts = <10>; + opencores,ip-clock-frequency = <20000000>; + + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ + + dummy@60 { + compatible = "dummy"; + reg = <0x60>; + }; + }; + + i2c@b0000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "opencores,i2c-ocores"; + reg = <0xa0000000 0x8>; + interrupts = <10>; + clocks = <&osc>; + clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ + + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ + + dummy@60 { + compatible = "dummy"; + reg = <0x60>; + }; + }; +...