diff mbox series

[3/3] arm64: dts: allwinner: a100: Add I2C DMA requests

Message ID 20220830020824.62288-4-samuel@sholland.org
State Accepted
Commit 5db5663cdf369b3575dae464cdcda0233ab19f44
Headers show
Series [1/3] dt-bindings: i2c: mv64xxx: Document DMA properties | expand

Commit Message

Samuel Holland Aug. 30, 2022, 2:08 a.m. UTC 
The I2C controllers in the A100 SoC are all connected to the DMA engine.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Jernej Škrabec Sept. 6, 2022, 9:11 p.m. UTC | #1 
Dne torek, 30. avgust 2022 ob 04:08:24 CEST je Samuel Holland napisal(a):
> The I2C controllers in the A100 SoC are all connected to the DMA engine.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej
Jernej Škrabec Sept. 8, 2022, 8:01 p.m. UTC | #2 
Dne torek, 06. september 2022 ob 23:11:02 CEST je Jernej Škrabec napisal(a):
> Dne torek, 30. avgust 2022 ob 04:08:24 CEST je Samuel Holland napisal(a):
> > The I2C controllers in the A100 SoC are all connected to the DMA engine.
> > 
> > Signed-off-by: Samuel Holland <samuel@sholland.org>
> 
> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Applied, thanks!

Best regards,
Jernej
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 5453a3bb7d81..97e3e6907acd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -221,6 +221,8 @@  i2c0: i2c@5002000 {
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C0>;
 			resets = <&ccu RST_BUS_I2C0>;
+			dmas = <&dma 43>, <&dma 43>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -234,6 +236,8 @@  i2c1: i2c@5002400 {
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C1>;
 			resets = <&ccu RST_BUS_I2C1>;
+			dmas = <&dma 44>, <&dma 44>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -247,6 +251,8 @@  i2c2: i2c@5002800 {
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C2>;
 			resets = <&ccu RST_BUS_I2C2>;
+			dmas = <&dma 45>, <&dma 45>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -260,6 +266,8 @@  i2c3: i2c@5002c00 {
 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C3>;
 			resets = <&ccu RST_BUS_I2C3>;
+			dmas = <&dma 46>, <&dma 46>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -337,6 +345,8 @@  r_i2c0: i2c@7081400 {
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&r_ccu CLK_R_APB2_I2C0>;
 			resets = <&r_ccu RST_R_APB2_I2C0>;
+			dmas = <&dma 50>, <&dma 50>;
+			dma-names = "rx", "tx";
 			pinctrl-names = "default";
 			pinctrl-0 = <&r_i2c0_pins>;
 			status = "disabled";
@@ -352,6 +362,8 @@  r_i2c1: i2c@7081800 {
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&r_ccu CLK_R_APB2_I2C1>;
 			resets = <&r_ccu RST_R_APB2_I2C1>;
+			dmas = <&dma 51>, <&dma 51>;
+			dma-names = "rx", "tx";
 			pinctrl-names = "default";
 			pinctrl-0 = <&r_i2c1_pins>;
 			status = "disabled";