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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id w9-20020a05600018c900b002c5a1bd5280sm12434670wrq.95.2023.03.07.04.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 04:41:16 -0800 (PST) From: Alexandre Mergnat Date: Tue, 07 Mar 2023 13:41:07 +0100 Subject: [PATCH v4 1/2] arm64: dts: mediatek: add i2c support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20221122-mt8365-i2c-support-v4-1-885ad3301d5a@baylibre.com> References: <20221122-mt8365-i2c-support-v4-0-885ad3301d5a@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v4-0-885ad3301d5a@baylibre.com> To: Rob Herring , Krzysztof Kozlowski , Qii Wang , Matthias Brugger Cc: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno , devicetree@vger.kernel.org, Alexandre Mergnat , Fabien Parent , Rob Herring , linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2699; i=amergnat@baylibre.com; h=from:subject:message-id; bh=u+MtjyWPgh4jPQn4QvtpwirJ4T/DfAOJHsOpg52IJ9U=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkBzDqCiWuVUZenZTJHFBYtVy0B5IyQnJXC+uVZ9IP OirqWTuJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZAcw6gAKCRArRkmdfjHURT4AD/ 9wYMx1vHjoOrKmlL7xjPDPSTvpxLJZf/NXsVj37zs7wt+ueBvxUem49Dxy1ChEA0UEip6Tt0x8r4tR Kd7nC8peqX2AoLfK7HFkiQ1QL8y1r1WC/IRQZofDQAwri2iN2TcTCaxKBiRttPQikbRycbw6xoR1Rq YvotJdmNGUOzxpi0lIURHfkWFSBG/2eNJRAr5cRXrxv1PkgXl7nGSNSNQU10P2pkXTA3+oE2FqxizR GGQNhUqN0PSzwnC3PsZomQgFCLnh+jj+yWgk3Ju6jSiDPdWFMYygAH7XiFtSNH6FrlODYqSDUZbiaC w3rRYdc25p47Q5W9d48jNpVvVguNx793pdG1Xqig5iYkGOID8+dJkza1mqQDSU/DB+R7PHt2WWxSNu kZlpVXSqgijHOqbYEE9jiKLSClpqHuKE10iODGIaYpQfVpCiNXNf+Ejz+iWdvuxguul+ta23esEnMU DVx9B5rcigh3xVI3nUOfybn8GqU+MCjHma5+m/bLOmIMHA4Ih3dh6PwT+laGOen53v/mH+jN9R1mLu XRcnvzSsk9v+FSW0b+yMeR8+6+mo4kRxtMhSbFho1HDCtbDdtGhcTf3fbHuI9/CfwNwnbAZgwnObPp bcLHAx37v+aHN4V1Q4UX8jT4Xe4WFNMj0yiu90hzQaqkKmUG//rn7BJlxAvg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org There are four I2C master channels in MT8365 with a same HW architecture. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 15ac4c1f0966..b70f4d256f63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -282,6 +282,42 @@ pwm: pwm@11006000 { clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi: spi@1100a000 { compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; reg = <0 0x1100a000 0 0x100>; @@ -295,6 +331,18 @@ spi: spi@1100a000 { status = "disabled"; }; + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ssusb: usb@11201000 { compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;