@@ -46,6 +46,11 @@ static const u32 fsi_base = 0xa0000000;
#define OPB_CLK_SYNC 0x3c
#define OPB_IRQ_CLEAR 0x40
#define OPB_IRQ_MASK 0x44
+/*
+ * This register does NOT behave in the expected manner. It is expected that writing 1b would clear
+ * the corresponding interrupt condition. However it also invisibly masks the interrupt! Writing 0b
+ * unmasks again.
+ */
#define OPB_IRQ_STATUS 0x48
#define OPB0_SELECT 0x10
@@ -64,8 +69,8 @@ static const u32 fsi_base = 0xa0000000;
#define OPB1_READ_ORDER2 0x60
#define OPB_RETRY_COUNTER 0x64
-#define OPB_RETRY_COUNTER_AST2600 0x00000010
-#define OPB_RETRY_COUNTER_AST2700 0x000c0010
+#define OPB_RETRY_COUNTER_AST2600 0x00010010
+#define OPB_RETRY_COUNTER_AST2700 0x000d0010
/* OPBn_STATUS */
#define STATUS_HALFWORD_ACK BIT(0)
@@ -107,13 +112,14 @@ static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr,
writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
writel_relaxed(addr, base + OPB0_FSI_ADDR);
writel_relaxed(val, base + OPB0_FSI_DATA_W);
- writel_relaxed(0x1, base + OPB_IRQ_CLEAR);
+ writel_relaxed(0, base + OPB_IRQ_STATUS);
writel(0x1, base + OPB_TRIGGER);
ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
(reg & OPB0_XFER_ACK_EN) != 0,
0, OPB_POLL_TIMEOUT);
+ writel(OPB0_XFER_ACK_EN, base + OPB_IRQ_STATUS);
status = readl(base + OPB0_STATUS);
/* Return error when poll timed out */
@@ -159,13 +165,14 @@ static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr,
writel_relaxed(CMD_READ, base + OPB0_RW);
writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
writel_relaxed(addr, base + OPB0_FSI_ADDR);
- writel_relaxed(0x1, base + OPB_IRQ_CLEAR);
+ writel_relaxed(0, aspeed->base + OPB_IRQ_STATUS);
writel(0x1, base + OPB_TRIGGER);
ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
(reg & OPB0_XFER_ACK_EN) != 0,
0, OPB_POLL_TIMEOUT);
+ writel(OPB0_XFER_ACK_EN, base + OPB_IRQ_STATUS);
status = readl(base + OPB0_STATUS);
result = readl(base + OPB0_FSI_DATA_R);
@@ -489,8 +496,6 @@ static int fsi_master_aspeed_probe(struct platform_device *pdev)
}
writel(0x1, aspeed->base + OPB_CLK_SYNC);
- writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN,
- aspeed->base + OPB_IRQ_MASK);
writel(opb_retry_counter, aspeed->base + OPB_RETRY_COUNTER);
In order to support FSI interrupts, the OPB transfer functions should not clear all the IRQs pending. Instead, just write the OPB ACK bit to the IRQ status register. As commented, this register invisibly masks the interrupt once the interrupt condition is cleared. Fix this by writing 0 before each OPB transfer. Signed-off-by: Eddie James <eajames@linux.ibm.com> --- drivers/fsi/fsi-master-aspeed.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)