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Thu, 30 Jan 2025 06:34:56 -0800 From: Kartik Rajput To: , , , , , , , , , , , , Subject: [PATCH v2 4/5] i2c: tegra: Add support for SW mutex register Date: Thu, 30 Jan 2025 20:04:23 +0530 Message-ID: <20250130143424.52389-5-kkartik@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250130143424.52389-1-kkartik@nvidia.com> References: <20250130143424.52389-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|CY8PR12MB8315:EE_ X-MS-Office365-Filtering-Correlation-Id: f92fc60d-7c12-45a4-2890-08dd413b513f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|82310400026|1800799024|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: WavUVM3HES9KIjKC0X2UUj5wR26y2D5U1GV+XNsf/NeBTnneLWrNJRMkGq72cvFSDW1qicMJ3o8meyqVSODHvcotTLI8LIKYWHskIsbY/cKb5dvnypfO1eyaLkT2tPW3SK8FcmV6WhIk5E8ghGT40xW7HYFN6DEJKgyKmXkd/OWxbhT30Fn6A+zZi6fuxSBZT4HOnhw7dUeBt/ovaKWbHedzhbLsGnPahKAk84/NoAcS4JUjwh52xfGdX54/50eEy6//J0BUuM6R+CI4EWIyXpaxCSGee4EquTcbKnUWKvnHfbfLVSwyXKhtbWodr5Gk8A4ZI+37ChBQGhS3Sjib52kY3U2TGSmCaIZ7pGUTVbcaZuEBBI2vPEHaDdHBr9iU8XEkWuuYqqwQq87vCH7aA33H+k7/0fVaj/GVaSP9h1Ruos5k16ZqKbEvbQZHScMc3Fq7wGHfI4ET5RTR4BqtTbhqsHbC75h+x28pZXKCU7OEDBNkFL2g86oifow9Y4D9IAjpRB3A9We4eriBGTb6NG5zB0f/LY7+Zg0eL+9vzUqjitcbjcb7Ezoz5IeDEOxrBdRPPL4ibJETlZpMD3t7CzYaSq/hEeUTAeAf+LsztnaoTlu8AyRwoWf61yTODvD5mPm7uYf3qy+C375XaZJbP4e7KhCu50y1GLd2TF8oTRWFwyvoMgu/atUlLNHWHULk0MDSCm5W0IgW+ZmiIjz4O4/QSn7s8cH0DG/dhaLoR7BWXiF4zHRazux2ApQ5welo1i4MHiwOAEcaam5aOo1ZE9gHg0jW82Ua1yByrQHUcsJFbDZe+blqRBBPuRqCBINDDPqkTKDCUkjaVzdNsoHOTkc0wUWaS8h7Z0yPlN3AcLURm13xjOLGxgdpF4Z6EQG8W/bugW4oTI7B3MKiYMczVN+165+mYDWMjc9Zp10AR+Zaiq/fzRMfHjLr8FFuwYpCO8/y27+1+aEXxBJLc4mlsh5CPliCb71yjLOj3wHJ7GGp5nSjSVD25N1NGo1J4cD4taxHxwb5su/VPZ7WCat9Vv4qjxMZJ7FMdJHVo6hXOmJRNvlG4771sm+viWhvG7KPtXr4lWqwhaIRhPjoDqzJ5H7AHYMYrY90gJElKAIyj+MEKHkswxFAINWdVaPUuPdiSq50+VieDbECApL9H0SudPtjIt67f47w9WRRA2mi3SZstqBeH/IeHFsiRaKCMa5P7+djfZGhsK1fmYnrN4JLfI92UQRk7wVwNIFhFKnZHmb9f06o4RNOnECDO2MGze2ui50HBrt3pb+2oobqhHLKa7dJtDeI0A3jZ6QffxzXHPX4Pq4PiafdUjGlFoLF9s65RkgwoSZfKRkNIrAS9LrUIhcCZ7/QktfQzJhqtQwOnj4kcWTKkmvDDVDWWP0RXcFfkvMPFv4DuEsRjb4w4Nv4Kmi8OukemCz7p6bxpAezVxIJdjywbUZYt2u3O926t14cQnk1Of3paKOJhOMlpEkSaw2B29Wm9xzxUvO8vkfLvsV/JlS2IJaY6+YL2NNKD3eL X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014)(7416014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jan 2025 14:35:17.6885 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f92fc60d-7c12-45a4-2890-08dd413b513f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8315 From: Akhil R Add support for SW mutex register introduced in Tegra264 to provide an option to share the interface between multiple firmwares and/or VMs. However, the hardware does not ensure any protection based on the values. The driver/firmware should honor the peer who already holds the mutex. Signed-off-by: Akhil R Signed-off-by: Kartik Rajput --- v1 -> v2: * Fixed typos. * Fix tegra_i2c_mutex_lock() logic. * Add a timeout in tegra_i2c_mutex_lock() instead of polling for mutex indefinitely. --- drivers/i2c/busses/i2c-tegra.c | 132 +++++++++++++++++++++++++++++---- 1 file changed, 117 insertions(+), 15 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 7c8b76406e2e..aa92faa6f5cb 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -135,6 +135,14 @@ #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) +#define I2C_SW_MUTEX 0x0ec +#define I2C_SW_MUTEX_REQUEST GENMASK(3, 0) +#define I2C_SW_MUTEX_GRANT GENMASK(7, 4) +#define I2C_SW_MUTEX_ID 9 + +/* SW mutex acquire timeout value in milliseconds. */ +#define I2C_SW_MUTEX_TIMEOUT 25 + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 @@ -203,6 +211,7 @@ enum msg_end_type { * @has_interface_timing_reg: Has interface timing register to program the tuned * timing settings. * @has_hs_mode_support: Has support for high speed (HS) mode transfers. + * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VM. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -229,6 +238,7 @@ struct tegra_i2c_hw_feature { u32 setup_hold_time_hs_mode; bool has_interface_timing_reg; bool has_hs_mode_support; + bool has_mutex; }; /** @@ -372,6 +382,103 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); } +static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, + u32 reg, u32 mask, u32 delay_us, + u32 timeout_us) +{ + void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); + u32 val; + + if (!i2c_dev->atomic_mode) + return readl_relaxed_poll_timeout(addr, val, !(val & mask), + delay_us, timeout_us); + + return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), + delay_us, timeout_us); +} + +static int tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev) +{ + u32 val, id; + + val = i2c_readl(i2c_dev, I2C_SW_MUTEX); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + if (id != 0 && id != I2C_SW_MUTEX_ID) + return 0; + + val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID); + i2c_writel(i2c_dev, val, I2C_SW_MUTEX); + + val = i2c_readl(i2c_dev, I2C_SW_MUTEX); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + if (id != I2C_SW_MUTEX_ID) + return 0; + + return 1; +} + +static void tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev) +{ + unsigned int num_retries = I2C_SW_MUTEX_TIMEOUT; + + /* Poll until mutex is acquired or timeout. */ + while (--num_retries && !tegra_i2c_mutex_trylock(i2c_dev)) + usleep_range(1000, 2000); + + WARN_ON(!num_retries); +} + +static void tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev) +{ + u32 val, id; + + val = i2c_readl(i2c_dev, I2C_SW_MUTEX); + id = FIELD_GET(I2C_SW_MUTEX_GRANT, val); + + if (WARN_ON(id != I2C_SW_MUTEX_ID)) + return; + + i2c_writel(i2c_dev, 0, I2C_SW_MUTEX); +} + +static void tegra_i2c_bus_lock(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); + + rt_mutex_lock_nested(&adapter->bus_lock, i2c_adapter_depth(adapter)); + tegra_i2c_mutex_lock(i2c_dev); +} + +static int tegra_i2c_bus_trylock(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); + int ret; + + ret = rt_mutex_trylock(&adapter->bus_lock); + if (ret) + ret = tegra_i2c_mutex_trylock(i2c_dev); + + return ret; +} + +static void tegra_i2c_bus_unlock(struct i2c_adapter *adapter, + unsigned int flags) +{ + struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); + + rt_mutex_unlock(&adapter->bus_lock); + tegra_i2c_mutex_unlock(i2c_dev); +} + +static const struct i2c_lock_operations tegra_i2c_lock_ops = { + .lock_bus = tegra_i2c_bus_lock, + .trylock_bus = tegra_i2c_bus_trylock, + .unlock_bus = tegra_i2c_bus_unlock, +}; + static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) { u32 int_mask; @@ -550,21 +657,6 @@ static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev) i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT); } -static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev, - u32 reg, u32 mask, u32 delay_us, - u32 timeout_us) -{ - void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); - u32 val; - - if (!i2c_dev->atomic_mode) - return readl_relaxed_poll_timeout(addr, val, !(val & mask), - delay_us, timeout_us); - - return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask), - delay_us, timeout_us); -} - static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) { u32 mask, val, offset; @@ -1503,6 +1595,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { @@ -1527,6 +1620,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { @@ -1551,6 +1645,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = false, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { @@ -1575,6 +1670,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0x0, .setup_hold_time_hs_mode = 0x0, .has_interface_timing_reg = true, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { @@ -1599,6 +1695,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0, .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { @@ -1623,6 +1720,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .setup_hold_time_fast_fast_plus_mode = 0, .setup_hold_time_hs_mode = 0, .has_interface_timing_reg = true, + .has_mutex = false, }; static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { @@ -1650,6 +1748,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .setup_hold_time_hs_mode = 0x090909, .has_interface_timing_reg = true, .has_hs_mode_support = true, + .has_mutex = false, }; static const struct of_device_id tegra_i2c_of_match[] = { @@ -1853,6 +1952,9 @@ static int tegra_i2c_probe(struct platform_device *pdev) i2c_dev->adapter.nr = pdev->id; ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev)); + if (i2c_dev->hw->has_mutex) + i2c_dev->adapter.lock_ops = &tegra_i2c_lock_ops; + if (i2c_dev->hw->supports_bus_clear) i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;