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Tue, 6 May 2025 03:00:03 -0700 From: Akhil R To: , , , , , , , , , , , , CC: Akhil R Subject: [PATCH 2/4] i2c: tegra: make reset an optional property Date: Tue, 6 May 2025 15:29:34 +0530 Message-ID: <20250506095936.10687-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20250506095936.10687-1-akhilrajeev@nvidia.com> References: <20250506095936.10687-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|DS7PR12MB6143:EE_ X-MS-Office365-Filtering-Correlation-Id: 4258dc2f-b406-4966-9cf0-08dd8c84d251 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|7416014|376014|82310400026|921020; X-Microsoft-Antispam-Message-Info: edCQBQp850zFvJD0lHhfAQgccH1i4oNM7mRi7qeehQqCU8uV137zOIMhPYKI7BAAaelv+KsymBEYXplu0vBLQR+rwD8zSDORZVhZgsafyIhO/mXJoxcXxRQBYa4EPdsQ27rd/HgADGwL6oaztYWO4BoXWtkKfkICwN/FNzflSTrpWINIYZXPHKutkWGNBmYKCIdA1a3k16G/ssKMzJ/NNYsyLfnfCsMHKnCMyGriUE28HDTF/SitcLP/fyX4AWaolG27YZaBFIm3Ib30qkkQPMW22c3Qx31mrECg+7ObryFVeW0iwRG66fBbpoj0w+mz6MiDPzWOZIjyORvhiBwAOA42DmuVtp/zZIqavX/1Gtsd9hG06SD2tEAQA0F8LMO4kLvdpY1KD041WSDi4hv17PnIWRqOKOxU1QNW0l8BAQZrER7g3HbnqLFgNlYohElqAdMyQCyEiNm5jXS+JSQ6ayVE2AbZXY3Ur+45SuSTKF9ZeKK1LoFTr4ZAGRwzWI2HyB3hJ08l5jdmMVJcEtXzxF9daazxfdq+2fQb2C4a6yOSaShAM6gzozdmUZEkJCHydH8TEruiYSLyIC6VKqke8aUTr4EyTXqE9777Iy5xIJq6C6jabhUbi2CaMqzBg1LifE3Gi49UTkaJm7vCAvUSIFq0y98gHEAagV0U+Bx7JCMa1LctsvFKScAdrc24v8T/V9h6I2swUVAEDN7kJkV+cZK7et6ej7JODPpqok0pK/ZQ6UEMgyxO6KPBAVWaVDsFWq6wk8HOddK9z+sSuJ23czhh2G6X/7Tmo9thQhb/PF5+VV3EpjymCsnZXeTgM+XxH92TVcAOPuwm59B1J8yl0RNfBv8YWnb87jQxySWpIC2RifMM2d3BlENvbNXOKzuf9puS3RYWwFUeKcmWQ+G3lpwIbBGaHT4lZBJ6mIjOkCK3pH8O/OZMYxFd3i9uipLW9z27CXKlyF6b0ukVBeKHaV0zl3kjRDN7VyYH4hSCv4UtgmKp2F50CdThnuTx2thN+6jqNtxLNqA4y7KubDfliBfplJ38kBfsYjAGixhRU7cw5svRQDJZIzNRI3HLmAef4lXbKS84yCYhB6tZksvpyCnp7GXLldZGKm1HzES5xU3q7PeV2hmXYyQfk1vvDBZFCMLavZ2MOjvNP5FLcEjiYbqjUrJovI78SMf15uLCMass/A4MLDvfoYhpXFDYflACjGULYQMkeKG0nLzLlPmdNavIqWMeDHqePcIhXZR3eDWHktGWcjgOncuxI1EhTDt6EcpmDf5HHQ7BI6V7FOeH+0KZ6m383KnYR4BhOJcSKtClviYYqqtAAkx04FNBm/dzO1VByaK9BS3KE8ttFqHjXYD+fZYCyJvUfMgi8FgyXD5wOv/JNyd+/gjvn0F6/gpp2r5DYKLXnkf8H/hJTJfBufXneMT8ArNoMpzKqF/OsvVHMG1t7sV0PaJG0sdeTSiQjxgk2r7peqjYN0x+uxYhaN9VeADkpnbCo+QuvoffOftn/l5x5SiiENP1LoDpeaCUSWCUF3YFTM99KBa29xa1Vg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(7416014)(376014)(82310400026)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2025 10:00:24.7070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4258dc2f-b406-4966-9cf0-08dd8c84d251 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6143 For controllers that has an internal software reset, make the reset property optional. This is useful in systems that choose to restrict reset control from Linux. Signed-off-by: Akhil R --- drivers/i2c/busses/i2c-tegra.c | 35 ++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 87976e99e6d0..49b77dcef184 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -134,6 +134,8 @@ #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) +#define I2C_MASTER_RESET_CNTRL 0x0a8 + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 @@ -184,6 +186,9 @@ enum msg_end_type { * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that * provides additional features and allows for longer messages to * be transferred in one go. + * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which + * provides an alternative to controller reset when configured as + * I2C master * @quirks: I2C adapter quirks for limiting write/read transfer size and not * allowing 0 length transfers. * @supports_bus_clear: Bus Clear support to recover from bus hang during @@ -213,6 +218,7 @@ struct tegra_i2c_hw_feature { bool has_multi_master_mode; bool has_slcg_override_reg; bool has_mst_fifo; + bool has_mst_reset; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; bool has_apb_dma; @@ -604,6 +610,18 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) return 0; } +static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev) +{ + if (!i2c_dev->hw->has_mst_reset) + return -EOPNOTSUPP; + + i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL); + udelay(1); + i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL); + + return 0; +} + static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; @@ -621,8 +639,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) */ if (handle) err = acpi_evaluate_object(handle, "_RST", NULL, NULL); - else + else if (i2c_dev->rst) err = reset_control_reset(i2c_dev->rst); + else + err = tegra_i2c_master_reset(i2c_dev); WARN_ON_ONCE(err); @@ -1467,6 +1487,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1491,6 +1512,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = false, .has_apb_dma = true, @@ -1515,6 +1537,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = false, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1539,6 +1562,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1563,6 +1587,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = true, @@ -1587,6 +1612,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { .has_multi_master_mode = false, .has_slcg_override_reg = true, .has_mst_fifo = false, + .has_mst_reset = false, .quirks = &tegra_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1611,6 +1637,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { .has_multi_master_mode = true, .has_slcg_override_reg = true, .has_mst_fifo = true, + .has_mst_reset = true, .quirks = &tegra194_i2c_quirks, .supports_bus_clear = true, .has_apb_dma = false, @@ -1666,7 +1693,11 @@ static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) if (ACPI_HANDLE(i2c_dev->dev)) return 0; - i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); + if (i2c_dev->hw->has_mst_reset) + i2c_dev->rst = devm_reset_control_get_optional_exclusive(i2c_dev->dev, "i2c"); + else + i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); + if (IS_ERR(i2c_dev->rst)) return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), "failed to get reset control\n");