| Message ID | 20250530143135.366417-5-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add RIIC support for RZ/T2H and RZ/N2H SoCs | expand |
On Fri, May 30, 2025 at 03:31:33PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs, > which feature a combined error interrupt instead of individual error > interrupts per condition, update the driver to support configurable IRQ > layouts via OF data. > > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to > allow future SoCs to provide a custom IRQ layout. This patch is a > non-functional change for existing SoCs and maintains compatibility with > the current `riic_irqs` array. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Did you test this on RZ/A1? I could do so next week?
Hi Wolfram, Thank you for the review. On Sat, May 31, 2025 at 1:12 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > > On Fri, May 30, 2025 at 03:31:33PM +0100, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs, > > which feature a combined error interrupt instead of individual error > > interrupts per condition, update the driver to support configurable IRQ > > layouts via OF data. > > > > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to > > allow future SoCs to provide a custom IRQ layout. This patch is a > > non-functional change for existing SoCs and maintains compatibility with > > the current `riic_irqs` array. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > > Did you test this on RZ/A1? I could do so next week? > Unfortunately, I haven’t been able to test this on the RZ/A1 as I don’t have access to the hardware. If you’re able to run it next week, that would be really helpful. Cheers, Prabhakar
On Fri, May 30, 2025 at 03:31:33PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs, > which feature a combined error interrupt instead of individual error > interrupts per condition, update the driver to support configurable IRQ > layouts via OF data. > > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to > allow future SoCs to provide a custom IRQ layout. This patch is a > non-functional change for existing SoCs and maintains compatibility with > the current `riic_irqs` array. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # on RZ/A1
On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs, > which feature a combined error interrupt instead of individual error > interrupts per condition, update the driver to support configurable IRQ > layouts via OF data. > > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to > allow future SoCs to provide a custom IRQ layout. This patch is a > non-functional change for existing SoCs and maintains compatibility with > the current `riic_irqs` array. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> No regressions on RZ/A1H, RZ/A2M, and RZ/Five, so Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hi Prabhakar, On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs, > which feature a combined error interrupt instead of individual error > interrupts per condition, update the driver to support configurable IRQ > layouts via OF data. > > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to > allow future SoCs to provide a custom IRQ layout. This patch is a > non-functional change for existing SoCs and maintains compatibility with > the current `riic_irqs` array. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > drivers/i2c/busses/i2c-riic.c | 22 ++++++++++++++++------ > 1 file changed, 16 insertions(+), 6 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c > index 23375f7fe3ad..4950b790cfe7 100644 > --- a/drivers/i2c/busses/i2c-riic.c > +++ b/drivers/i2c/busses/i2c-riic.c > @@ -102,6 +102,8 @@ enum riic_reg_list { > > struct riic_of_data { > const u8 *regs; > + const struct riic_irq_desc *irqs; > + u8 num_irqs; > bool fast_mode_plus; > }; > > @@ -607,10 +611,14 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { > static const struct riic_of_data riic_rz_a_info = { > .regs = riic_rz_a_regs, > .fast_mode_plus = true, > + .irqs = riic_irqs, > + .num_irqs = ARRAY_SIZE(riic_irqs), Nit: Perhaps initialize the members in the order of declaration? > }; > > static const struct riic_of_data riic_rz_a1h_info = { > .regs = riic_rz_a_regs, > + .irqs = riic_irqs, > + .num_irqs = ARRAY_SIZE(riic_irqs), > }; > > static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { > @@ -631,6 +639,8 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { > static const struct riic_of_data riic_rz_v2h_info = { > .regs = riic_rz_v2h_regs, > .fast_mode_plus = true, > + .irqs = riic_irqs, > + .num_irqs = ARRAY_SIZE(riic_irqs), Likewise. > }; > > static int riic_i2c_suspend(struct device *dev) Gr{oetje,eeting}s, Geert
Hi Geert, Thank you for the review. On Fri, Jun 6, 2025 at 2:26 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Fri, 30 May 2025 at 16:31, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > In preparation for adding support for Renesas RZ/T2H and RZ/N2H SoCs, > > which feature a combined error interrupt instead of individual error > > interrupts per condition, update the driver to support configurable IRQ > > layouts via OF data. > > > > Introduce a new `irqs` field and `num_irqs` count in `riic_of_data` to > > allow future SoCs to provide a custom IRQ layout. This patch is a > > non-functional change for existing SoCs and maintains compatibility with > > the current `riic_irqs` array. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > drivers/i2c/busses/i2c-riic.c | 22 ++++++++++++++++------ > > 1 file changed, 16 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c > > index 23375f7fe3ad..4950b790cfe7 100644 > > --- a/drivers/i2c/busses/i2c-riic.c > > +++ b/drivers/i2c/busses/i2c-riic.c > > @@ -102,6 +102,8 @@ enum riic_reg_list { > > > > struct riic_of_data { > > const u8 *regs; > > + const struct riic_irq_desc *irqs; > > + u8 num_irqs; > > bool fast_mode_plus; > > }; > > > > > @@ -607,10 +611,14 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { > > static const struct riic_of_data riic_rz_a_info = { > > .regs = riic_rz_a_regs, > > .fast_mode_plus = true, > > + .irqs = riic_irqs, > > + .num_irqs = ARRAY_SIZE(riic_irqs), > > Nit: Perhaps initialize the members in the order of declaration? > Ok, I will fix this in the next version (and below too). Cheers, Prabhakar
diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 23375f7fe3ad..4950b790cfe7 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -102,6 +102,8 @@ enum riic_reg_list { struct riic_of_data { const u8 *regs; + const struct riic_irq_desc *irqs; + u8 num_irqs; bool fast_mode_plus; }; @@ -520,21 +522,23 @@ static int riic_i2c_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(riic->rstc), "failed to acquire deasserted reset\n"); - for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) { + riic->info = of_device_get_match_data(dev); + + for (i = 0; i < riic->info->num_irqs; i++) { + const struct riic_irq_desc *irq_desc; int irq; - irq = platform_get_irq(pdev, riic_irqs[i].res_num); + irq_desc = &riic->info->irqs[i]; + irq = platform_get_irq(pdev, irq_desc->res_num); if (irq < 0) return irq; - ret = devm_request_irq(dev, irq, riic_irqs[i].isr, - 0, riic_irqs[i].name, riic); + ret = devm_request_irq(dev, irq, irq_desc->isr, 0, irq_desc->name, riic); if (ret) return dev_err_probe(dev, ret, "failed to request irq %s\n", - riic_irqs[i].name); + irq_desc->name); } - riic->info = of_device_get_match_data(dev); adap = &riic->adapter; i2c_set_adapdata(adap, riic); @@ -607,10 +611,14 @@ static const u8 riic_rz_a_regs[RIIC_REG_END] = { static const struct riic_of_data riic_rz_a_info = { .regs = riic_rz_a_regs, .fast_mode_plus = true, + .irqs = riic_irqs, + .num_irqs = ARRAY_SIZE(riic_irqs), }; static const struct riic_of_data riic_rz_a1h_info = { .regs = riic_rz_a_regs, + .irqs = riic_irqs, + .num_irqs = ARRAY_SIZE(riic_irqs), }; static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { @@ -631,6 +639,8 @@ static const u8 riic_rz_v2h_regs[RIIC_REG_END] = { static const struct riic_of_data riic_rz_v2h_info = { .regs = riic_rz_v2h_regs, .fast_mode_plus = true, + .irqs = riic_irqs, + .num_irqs = ARRAY_SIZE(riic_irqs), }; static int riic_i2c_suspend(struct device *dev)