From patchwork Mon Jan 16 16:04:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 643281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33A63C54EBE for ; Mon, 16 Jan 2023 16:09:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232149AbjAPQJQ (ORCPT ); Mon, 16 Jan 2023 11:09:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232483AbjAPQIW (ORCPT ); Mon, 16 Jan 2023 11:08:22 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B382822A0E; Mon, 16 Jan 2023 08:05:59 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 3664FB81065; Mon, 16 Jan 2023 16:05:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25FDFC433EF; Mon, 16 Jan 2023 16:05:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673885156; bh=A2lMnNpwS6S66/IQOfPFdDu2/4XhxRCJbXbHkSaZYLQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Ia3VNl7Q0DH7gaJ4mpSKEw+FvMPuvtkQ4nWizcmTV1ICD0u1dOEGzaq0U4WGcFCqV lCYH4m0kYzYwUqwTey2JJX9cZ1C/OiNri07/ve4nIa1ZyHX9vXAFlTfQo224sX6McQ ZnA4lqjc4uDfDQgUUF51KOVOQAQOqOgZAX20q8GuAP9hGHIFPJ30l8ysP9RspMPo9z 3qDYou7iD/qJ9yqJq4QUKfns5qiTGmd2FQbZPw1fjoPBxuqSoNAAvQbMkd5D7+9p8W R0LHOcs1Jib2VoDdH9SH+V1q15gBV09nSub/FoeU/7GMAdaMKCM1Yy57ebE9AiIq57 IVfhNSEsykZ8Q== From: Mark Brown Date: Mon, 16 Jan 2023 16:04:42 +0000 Subject: [PATCH v4 07/21] arm64/sme: Enable host kernel to access ZT0 MIME-Version: 1.0 Message-Id: <20221208-arm64-sme2-v4-7-f2fa0aef982f@kernel.org> References: <20221208-arm64-sme2-v4-0-f2fa0aef982f@kernel.org> In-Reply-To: <20221208-arm64-sme2-v4-0-f2fa0aef982f@kernel.org> To: Catalin Marinas , Will Deacon , Oleg Nesterov , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Oliver Upton , Shuah Khan Cc: Alan Hayward , Luis Machado , Szabolcs Nagy , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.12-dev-77e06 X-Developer-Signature: v=1; a=openpgp-sha256; l=1460; i=broonie@kernel.org; h=from:subject:message-id; bh=A2lMnNpwS6S66/IQOfPFdDu2/4XhxRCJbXbHkSaZYLQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBjxXWnTp5ZGErr4lpzXbWz2naqNeSyfqHWUbeT68Dg 1kDpfYiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCY8V1pwAKCRAk1otyXVSH0FmsB/ 9usXcD+QpmmUQlVUPN6H/k4eWHLR4r3VwhBTI8+6H4bvluQqNUziGccjwm1TiSGdgS+S1OT7H6pNck WgJZ14DIivBBaWX9AN9uSycMS08b1xTQqAwyiD0Smosu4eztdGdmHuFDiLUkvrerA9+6xGgs+YZrcg EO4onn9BPWowPQVnI29JHJtVbVcvJyx/p7L+xrPJnGIVdgS2r+ISh2aZGl+oskJ4R+MKTPUAvCwBWG 5zVsubXATcOz4m5XTWwoAeZ+MqkwacbKJyLE5OxIgkL1mAe0N2+32qVp7dg9HTPc4OEnb6O0Dz+CgW kVyHsqJweSqqtZYU2lTXxxl5ZyDiNQ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The new register ZT0 introduced by SME2 comes with a new trap, disable it for the host kernel so that we can implement support for it. Signed-off-by: Mark Brown Signed-off-by: Marc Zyngier Reviewed-by: Mark Brown --- arch/arm64/kernel/hyp-stub.S | 6 ++++++ arch/arm64/kernel/idreg-override.c | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index 2ee18c860f2a..d31d1acb170d 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -132,6 +132,12 @@ SYM_CODE_START_LOCAL(__finalise_el2) orr x0, x0, SMCR_ELx_FA64_MASK .Lskip_sme_fa64: + // ZT0 available? + __check_override id_aa64smfr0 ID_AA64SMFR0_EL1_SMEver_SHIFT 4 .Linit_sme_zt0 .Lskip_sme_zt0 +.Linit_sme_zt0: + orr x0, x0, SMCR_ELx_EZT0_MASK +.Lskip_sme_zt0: + orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector msr_s SYS_SMCR_EL2, x0 // length for EL1. diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c index 95133765ed29..d833d78a7f31 100644 --- a/arch/arm64/kernel/idreg-override.c +++ b/arch/arm64/kernel/idreg-override.c @@ -131,6 +131,7 @@ static const struct ftr_set_desc smfr0 __initconst = { .name = "id_aa64smfr0", .override = &id_aa64smfr0_override, .fields = { + FIELD("smever", ID_AA64SMFR0_EL1_SMEver_SHIFT, NULL), /* FA64 is a one bit field... :-/ */ { "fa64", ID_AA64SMFR0_EL1_FA64_SHIFT, 1, }, {}