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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044FD.mail.protection.outlook.com (10.167.241.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7228.0 via Frontend Transport; Fri, 19 Jan 2024 09:06:06 +0000 Received: from jasmine-meng.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 19 Jan 2024 03:06:00 -0600 From: Meng Li To: "Rafael J . Wysocki" , Borislav Petkov , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny , Perry Yuan Subject: [PATCH V14 6/7] Documentation: amd-pstate: introduce amd-pstate preferred core Date: Fri, 19 Jan 2024 17:05:01 +0800 Message-ID: <20240119090502.3869695-7-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240119090502.3869695-1-li.meng@amd.com> References: <20240119090502.3869695-1-li.meng@amd.com> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FD:EE_|IA1PR12MB6627:EE_ X-MS-Office365-Filtering-Correlation-Id: 23bb918b-1c7c-45f6-c2ee-08dc18cddf17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: M59X0qZco7ehCSuwkubWjCw1LAYXCSpqcGmefN5Z81CJMLP6mwXZDH2i2ORCwTJEr7ml6s4uwJaQTaqAPlRLaLadDfDFq233qj++uzodJKNEvFy8wkdzsx3dp6O/9E5XXFoqS+oKz6enDOcQmDY/FYC6TT0/0gSvnycfyiheQUfbCn7N4/gPpaGRpJCOLp8mUPiAeeO5aezE5ZZC3rI5W0b5+wVPsn/6ovczoLi1+nobMAyIMVeScV+bAea6FYBbWAPyzZeL328wnbR83cnpJkvoQzXE5p7Lpg1tawjmTy7x46c2mQE1x+VkNcgN1RlrKjfcloTv6/NgSnzfMwItV+KnpXBChfQNG4h6VwB3s6nRHSXUCr0nhF7B5r4R05zJVSByjBnjQqCb1xRmh0JiiWwzonIfgkmmdND2fisRzIzSMOklHfsQDxEkt39tLnZcF0eq1+zGWMHPJuK1caOTHdKWEKHDyxUwiHzkGusFirjpjlDx6oUc+aBShIKC9XzfdmA/SdMjC49BiFIJvgTAJcDZCiBSROYuba47FfTOmeX9Zv4k7u92ixPGpN/YXLkueB2TZKiKXGkEOdtqzJ2jnP6j8g109rR2OBMljSHL7hsVue4OkCVpfhi0FD9+XK2FHhDf4F+AVVn77z+WB7LInDt3GvJsrtLB+ubGdunO13xty5tj48Ws1/Cj+cZNTopJgdNN/h/ZBhBH79na2/ZhEs98BpFZZr3qclmlfyB8qQLSwFGlu4TxkvdTaxT54divg380EtYgWOjCrXfcOSK2lw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(136003)(346002)(39860400002)(376002)(396003)(230922051799003)(64100799003)(1800799012)(451199024)(82310400011)(186009)(40470700004)(36840700001)(46966006)(40460700003)(40480700001)(336012)(426003)(81166007)(82740400003)(86362001)(36756003)(356005)(36860700001)(2906002)(5660300002)(83380400001)(26005)(2616005)(1076003)(16526019)(478600001)(47076005)(7696005)(4326008)(8676002)(8936002)(41300700001)(7416002)(110136005)(316002)(54906003)(6636002)(70586007)(70206006)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 09:06:06.8600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 23bb918b-1c7c-45f6-c2ee-08dc18cddf17 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6627 Introduce amd-pstate preferred core. check preferred core state set by the kernel parameter: $ cat /sys/devices/system/cpu/amd-pstate/prefcore Tested-by: Oleksandr Natalenko Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Reviewed-by: Perry Yuan Signed-off-by: Meng Li --- Documentation/admin-guide/pm/amd-pstate.rst | 59 ++++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 9eb26014d34b..0a3aa6b8ffd5 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -300,8 +300,8 @@ platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -AMD Pstate Driver Operation Modes -================================= +``amd-pstate`` Driver Operation Modes +====================================== ``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, non-autonomous (passive) mode and guided autonomous (guided) mode. @@ -353,6 +353,48 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +``amd-pstate`` Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``amd-pstate`` preferred core enables the scheduler to prefer scheduling on +cores that can achieve a higher frequency with lower voltage. The preferred +core rankings can dynamically change based on the workload, platform conditions, +thermals and ageing. + +The priority metric will be initialized by the ``amd-pstate`` driver. The ``amd-pstate`` +driver will also determine whether or not ``amd-pstate`` preferred core is +supported by the platform. + +``amd-pstate`` driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When ``amd-pstate`` +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +``amd-pstate`` Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``amd-pstate`` peferred core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default enable ``amd-pstate`` preferred core. + +``amd_prefcore=disable`` + +For systems that support ``amd-pstate`` preferred core, the core rankings will +always be advertised by the platform. But OS can choose to ignore that via the +kernel parameter ``amd_prefcore=disable``. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +427,19 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore`` + Preferred core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the ``amd-pstate`` preferred core. + + "disabled" + Disable the ``amd-pstate`` preferred core + + + This attribute is read-only to check the state of preferred core set + by the kernel parameter. + ``cpupower`` tool support for ``amd-pstate`` ===============================================