From patchwork Fri May 2 23:30:47 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 887305 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1E6826988E for ; Fri, 2 May 2025 23:31:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746228691; cv=none; b=cZwvUy9SVV1CCflCVGCrkQeyYfshylY57JlzOwRTrGMx/AyroIRRrRPX5OSMWCxjd1PyohI2Kioy0qdk15QaWVITodBnEEeaezxpCW7/i8LLw2U4gg5iCxNiyWFNQ7GtyhmhVAAUpcY5PJCz9OtbLjtzCXOS39SlZsKX13zY0nQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746228691; c=relaxed/simple; bh=sceMDvU8DoYKg5vxiA9YsPZLUrKbHYFHIRo8Vx6EGT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cMc/FqmgYQ2wK98Lr+haAtKULqsrhQCdTRXheXWTCOSeko+GP85OtDh+4Q7Dtpny2PjZ8Af/WojAv3Fjvl1zvCG3ROTHxfcFdREUud6gN6hjYKYkW10EwxeXEZVf/Gfrfb/xX6zkHEVVizzAmXprDQTRx4yKLb/kCyfk1oHTf2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=EoygS0tE; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="EoygS0tE" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-224100e9a5cso37003805ad.2 for ; Fri, 02 May 2025 16:31:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1746228689; x=1746833489; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+D4QltF1Nc7VEdA5n+UDPSlZueufWbEVbyRTdYC5Tzo=; b=EoygS0tEkBz0+PDubIXsuGyIiy5TJFZ9viGbMprfaoFxyXSU+WfxdGm2mPFV/nLSgq cJ8/Qz8sxoDlcm09riF8bIGWJQ0pOPtI7aYOtbzIAmXO2dyVt9AU2uT4ZgiQuMYeoOF3 3V1qEWD6rrnwlgkKwhf3GtJ3hs+dWoFCx7zQM9FcKCLPIRgnpLIxT9Kj+kY8r9lG6LQ8 U3uGExT8S5cfnoJp86MChNdnzFe2XcbscI8RfwY68bt6sm0EKbdnjKOsW6LX35AVwiJA suzga9v54DBi3lq2qjCyqtV4NpPOY27wMWMDUd7PAJtI33Yp8JCSErvdWzvL6CbmgWnT nDhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746228689; x=1746833489; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+D4QltF1Nc7VEdA5n+UDPSlZueufWbEVbyRTdYC5Tzo=; b=GnIOXVJDfGUmyYUoUcsjS4msNpcjjNOPTtO/u4qih8ipCX/HQAIvKpV1wN+63GlnLQ kVrxinikJcQvIa08FRsPmSwcfMFUs2XouxPCfx0dZjbXa9/jliyt46NnSxqrfVqLZFh/ xtBYO9V1NOjEWew5oWpvO79RZ3DtdIev4arY8+f5YHAkbgiyLu+zVa+annHwE/d4WN2W 8ELyJ7TM88FPWy8W+5p4EKHemoS/wBdQJE+N6rVcA51Nvzw0SKGT3emgNwz5ILV3qqwz DkPCm3embftxTLrV+8spFrNECHOt5egEcNxDx2daghjBNKlIyj6vy67iyAVzJXvPV7pQ X+xg== X-Forwarded-Encrypted: i=1; AJvYcCVqyrVu2axObXd0hRlnrJp3PKJ0cv5su6qpf2rC1pB6XqYfbD9jfdhqk7wmziwB6FgU33JtQ2RIOdQVXShhntM=@vger.kernel.org X-Gm-Message-State: AOJu0YxtUAsh3QCXch0fEcqcBzPXJD8O5nchS+3PSh85F8kGeKfWnJg7 IbK+RHBJozIECmyoWh7ZBpjJcrl2P1l1ry4tsfQMg4L6lnaggaaACl+tg3qPZoo= X-Gm-Gg: ASbGncuVXJyvlTZXcjqaLQhAil8QTN3Nnd2T+kaUnzkIu2LT7FtWCAsc+HHkz3Dz5yl 0pCLUpmpoOMszIQ3k4YNwxha4xiwpRrS05RW5k914D43qwxlG1O7hCyQymHN6cTeOukRcqZd66g B+5P+TUdZvBDau3iKTp3+5VzH2Brqt7vhVCsEoiV+qFJEY/7DgXmX1HbKQdMMthbQ9Lgcb48N9P nInoQ3H1x1xOdEO8+YTddH7l7xGWyYHLhVGZfd+aAz61L8YAuwgQu1S2BCaAMnCK0v2Z8GVv8oa rwwbJ2F+z86PmpSCl++OHKFJ6EB8Inq6sTgiiwjLokobPqiNie4= X-Google-Smtp-Source: AGHT+IGJ4hbkDrcvbzQ2C6CLIKfva5ov3ozZSff7DpG2Wz7f5TDK43zIBF2nqUREgeUFBJoDkj7ZjA== X-Received: by 2002:a17:903:228d:b0:224:721:ed9 with SMTP id d9443c01a7336-22e103aa1e0mr81004905ad.44.1746228689166; Fri, 02 May 2025 16:31:29 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e15228ff2sm13367055ad.180.2025.05.02.16.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 May 2025 16:31:28 -0700 (PDT) From: Deepak Gupta Date: Fri, 02 May 2025 16:30:47 -0700 Subject: [PATCH v15 16/27] riscv: signal: abstract header saving for setup_sigcontext Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250502-v5_user_cfi_series-v15-16-914966471885@rivosinc.com> References: <20250502-v5_user_cfi_series-v15-0-914966471885@rivosinc.com> In-Reply-To: <20250502-v5_user_cfi_series-v15-0-914966471885@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org X-Mailer: b4 0.13.0 From: Andy Chiu The function save_v_state() served two purposes. First, it saved extension context into the signal stack. Then, it constructed the extension header if there was no fault. The second part is independent of the extension itself. As a result, we can pull that part out, so future extensions may reuse it. This patch adds arch_ext_list and makes setup_sigcontext() go through all possible extensions' save() callback. The callback returns a positive value indicating the size of the successfully saved extension. Then the kernel proceeds to construct the header for that extension. The kernel skips an extension if it does not exist, or if the saving fails for some reasons. The error code is propagated out on the later case. This patch does not introduce any functional changes. Signed-off-by: Andy Chiu --- arch/riscv/include/asm/vector.h | 3 ++ arch/riscv/kernel/signal.c | 62 +++++++++++++++++++++++++++-------------- 2 files changed, 44 insertions(+), 21 deletions(-) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index e8a83f55be2b..05390538ea8a 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -407,6 +407,9 @@ static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } #define riscv_v_thread_free(tsk) do {} while (0) #define riscv_v_setup_ctx_cache() do {} while (0) #define riscv_v_thread_alloc(tsk) do {} while (0) +#define get_cpu_vector_context() do {} while (0) +#define put_cpu_vector_context() do {} while (0) +#define riscv_v_vstate_set_restore(task, regs) do {} while (0) #endif /* CONFIG_RISCV_ISA_V */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 08378fea3a11..a5e3d54fe54b 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -68,18 +68,19 @@ static long save_fp_state(struct pt_regs *regs, #define restore_fp_state(task, regs) (0) #endif -#ifdef CONFIG_RISCV_ISA_V - -static long save_v_state(struct pt_regs *regs, void __user **sc_vec) +static long save_v_state(struct pt_regs *regs, void __user *sc_vec) { - struct __riscv_ctx_hdr __user *hdr; struct __sc_riscv_v_state __user *state; void __user *datap; long err; - hdr = *sc_vec; - /* Place state to the user's signal context space after the hdr */ - state = (struct __sc_riscv_v_state __user *)(hdr + 1); + if (!IS_ENABLED(CONFIG_RISCV_ISA_V) || + !((has_vector() || has_xtheadvector()) && + riscv_v_vstate_query(regs))) + return 0; + + /* Place state to the user's signal context spac */ + state = (struct __sc_riscv_v_state __user *)sc_vec; /* Point datap right after the end of __sc_riscv_v_state */ datap = state + 1; @@ -97,15 +98,11 @@ static long save_v_state(struct pt_regs *regs, void __user **sc_vec) err |= __put_user((__force void *)datap, &state->v_state.datap); /* Copy the whole vector content to user space datap. */ err |= __copy_to_user(datap, current->thread.vstate.datap, riscv_v_vsize); - /* Copy magic to the user space after saving all vector conetext */ - err |= __put_user(RISCV_V_MAGIC, &hdr->magic); - err |= __put_user(riscv_v_sc_size, &hdr->size); if (unlikely(err)) - return err; + return -EFAULT; - /* Only progress the sv_vec if everything has done successfully */ - *sc_vec += riscv_v_sc_size; - return 0; + /* Only return the size if everything has done successfully */ + return riscv_v_sc_size; } /* @@ -142,10 +139,20 @@ static long __restore_v_state(struct pt_regs *regs, void __user *sc_vec) */ return copy_from_user(current->thread.vstate.datap, datap, riscv_v_vsize); } -#else -#define save_v_state(task, regs) (0) -#define __restore_v_state(task, regs) (0) -#endif + +struct arch_ext_priv { + __u32 magic; + long (*save)(struct pt_regs *regs, void __user *sc_vec); +}; + +struct arch_ext_priv arch_ext_list[] = { + { + .magic = RISCV_V_MAGIC, + .save = &save_v_state, + }, +}; + +const size_t nr_arch_exts = ARRAY_SIZE(arch_ext_list); static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) @@ -270,7 +277,8 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, { struct sigcontext __user *sc = &frame->uc.uc_mcontext; struct __riscv_ctx_hdr __user *sc_ext_ptr = &sc->sc_extdesc.hdr; - long err; + struct arch_ext_priv *arch_ext; + long err, i, ext_size; /* sc_regs is structured the same as the start of pt_regs */ err = __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); @@ -278,8 +286,20 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if ((has_vector() || has_xtheadvector()) && riscv_v_vstate_query(regs)) - err |= save_v_state(regs, (void __user **)&sc_ext_ptr); + for (i = 0; i < nr_arch_exts; i++) { + arch_ext = &arch_ext_list[i]; + if (!arch_ext->save) + continue; + + ext_size = arch_ext->save(regs, sc_ext_ptr + 1); + if (ext_size <= 0) { + err |= ext_size; + } else { + err |= __put_user(arch_ext->magic, &sc_ext_ptr->magic); + err |= __put_user(ext_size, &sc_ext_ptr->size); + sc_ext_ptr = (void *)sc_ext_ptr + ext_size; + } + } /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |= __put_user(0, &sc->sc_extdesc.reserved); /* And put END __riscv_ctx_hdr at the end. */