From patchwork Fri May 2 23:30:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Deepak Gupta X-Patchwork-Id: 887310 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B102225417 for ; Fri, 2 May 2025 23:30:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746228661; cv=none; b=k0E31+0vvDSmRvEOzY+6GT8jZHmhjJTixPKCUxGxhbcnlR48mh7xAVAnSVe8dEeAVye5GZEGgVHqdAJ3k7dHCl/rKhNl6OVXWOGM4jHWYUF2Zx70cTP+6FGRkdBEqntQqSEEDf0HT/lq8XI16qw9hqhngIKsy0Kd3BBDptm3LbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1746228661; c=relaxed/simple; bh=dgiqoDVtRvidZ666HdQoxDdMstst5+zplhPdm8ygATI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I1XhlRTvGNw4Mgq6YLw6rcLqC00WFhNBZVw9fknUM407JJRD9kC4JR3hfpOkmpajlj7CfSlSJP8Wr7dHXhBYkvRm4xbRpKHsji6rTdgjUkTj3SAnkbcO1LocQdh0ZViiXTzvu3FHNLrCDqoEygNSODb0JvW7eScs8dVJOhrQLbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=D9a/1kkL; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="D9a/1kkL" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-736c277331eso3573594b3a.1 for ; Fri, 02 May 2025 16:30:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1746228659; x=1746833459; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bllvdjgPqMLGFPevmb9vKr9B2wGZQF3J7YB/p9RdhJg=; b=D9a/1kkLMUSjYvlla4EI+3OzjgSQ7d6aT0PfKyK3VzIPxxpeD95uIIPuiP6/Hotd1l Is9YNEXUR5dtlFRi+FLaumWx+8dckVhiwoCkeuf1YdtsdNVmS7sTQSw0ouJGyT0dCkup ZpkhlGbRfZb/dkZTN0IPxGEwyeG4VY+QlfHKzEzXVvQ8IKmpyXXBqZIybwoVhabcOYso tfOwHkZyHrrCx2LvhfiSdUElb4wxu47HOD8o8LI6uNaDGPBZDP1r5LYThP0mL+gpSagq Wq0ewbe0E5LC+ZbQl8hlP4H3yeXT6oWegPM0lTFhlMSegq/ODs+3GF0mEztFbfIsBB8q OQIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1746228659; x=1746833459; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bllvdjgPqMLGFPevmb9vKr9B2wGZQF3J7YB/p9RdhJg=; b=mjHXdNQ2nptA1bm973iaO/v6JmXYT5aVXrz6zOkWC/9hkpDxoAKiQuWrciYiIwS7FS mzF88fVTm++cM4JlGMXvxeuImBMEUsru2XB7I9egtucWAG945/vfqbw0H8L3g+2QnuJF zvPSWhOIcavMTBcV0T1imfoYtH/aEMno786yex2Qy0GiZ7mcmXNrfEx+6Q8888WF8U8Q Bp4eYYxPIUZeEA4Qd7m/U6j8KYCfDv4Ttgk5VMorGcd5FHiVSBlCqRUPky9EJ6JNCLbC u5y7FW4ximepjstkhzoK6lOp183/fuLo1zulrFYS+/VQU9uOPb33mYn6bBZXY3DaBB2R bvAg== X-Forwarded-Encrypted: i=1; AJvYcCXSOZKt7J5O1HJQzNTXfrQldKNUFVZ6RQlgca28byJ/V4P1+Iq7+OPTbBvgYyvjUyh1c4hirtilfjpeRpZnpTw=@vger.kernel.org X-Gm-Message-State: AOJu0YwS/bx9B0oXRKeXmiitBGngvhduFTlIqAtNZf1Q9O3CqMbTdmY3 X9JFNxlMwnf4Ae/Lz/nUGGWLji09n4wZZXAkJlO99fGsCU5ezrGonXyFJuW0HL8= X-Gm-Gg: ASbGncvMS4w6JD06Wt74zZ74IdIsLDF7eExuE6Of0DQQi/X9Hfi8ztIrmVohQKOxlSn WqvYIoiAFCc6O0ZF6oXvNzn1/Ts5laCFdwp4MGSBXiKJG/N7pZhDZwyZMwlhehgFIE+eDwwZd2u YCHCr5ARl9F4LOUJ96Lacqb72VVs42LW+7tz7tK1GmtrAEjT/Rv1CKy/LDyeFdHoVYxlApY20Qf DexRF/T1f26RMpL1kUBxjlKahb/agujKb0eitDfYrYeOc5wuTV86widebUlBNpqKKTlPWLJ5fSb GiaqOfugSXUh5+yBTcfLP1ifHERMDYBznUCDyD8CYCl+L0ULIqQ= X-Google-Smtp-Source: AGHT+IE4ZkG/27hO5RQDKoxERYjQIr0cMAZhksKWIFN4zGbwE35WXTZLAwKltp7Gw8EDClWnBWZAWA== X-Received: by 2002:a17:90b:498c:b0:309:f46e:a67c with SMTP id 98e67ed59e1d1-30a4e228371mr7740624a91.11.1746228658917; Fri, 02 May 2025 16:30:58 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22e15228ff2sm13367055ad.180.2025.05.02.16.30.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 May 2025 16:30:58 -0700 (PDT) From: Deepak Gupta Date: Fri, 02 May 2025 16:30:37 -0700 Subject: [PATCH v15 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250502-v5_user_cfi_series-v15-6-914966471885@rivosinc.com> References: <20250502-v5_user_cfi_series-v15-0-914966471885@rivosinc.com> In-Reply-To: <20250502-v5_user_cfi_series-v15-0-914966471885@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 `arch_calc_vm_prot_bits` is implemented on risc-v to return VM_READ | VM_WRITE if PROT_WRITE is specified. Similarly `riscv_sys_mmap` is updated to convert all incoming PROT_WRITE to (PROT_WRITE | PROT_READ). This is to make sure that any existing apps using PROT_WRITE still work. Earlier `protection_map[VM_WRITE]` used to pick read-write PTE encodings. Now `protection_map[VM_WRITE]` will always pick PAGE_SHADOWSTACK PTE encodings for shadow stack. Above changes ensure that existing apps continue to work because underneath kernel will be picking `protection_map[VM_WRITE|VM_READ]` PTE encodings. Reviewed-by: Zong Li Reviewed-by: Alexandre Ghiti Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/mman.h | 25 +++++++++++++++++++++++++ arch/riscv/include/asm/pgtable.h | 1 + arch/riscv/kernel/sys_riscv.c | 10 ++++++++++ arch/riscv/mm/init.c | 2 +- 4 files changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/mman.h b/arch/riscv/include/asm/mman.h new file mode 100644 index 000000000000..392c9c2d2e78 --- /dev/null +++ b/arch/riscv/include/asm/mman.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_MMAN_H__ +#define __ASM_MMAN_H__ + +#include +#include +#include + +static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot, + unsigned long pkey __always_unused) +{ + unsigned long ret = 0; + + /* + * If PROT_WRITE was specified, force it to VM_READ | VM_WRITE. + * Only VM_WRITE means shadow stack. + */ + if (prot & PROT_WRITE) + ret = (VM_READ | VM_WRITE); + return ret; +} + +#define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey) + +#endif /* ! __ASM_MMAN_H__ */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 428e48e5f57d..dba257cc4e2d 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -182,6 +182,7 @@ extern struct pt_alloc_ops pt_ops __meminitdata; #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ _PAGE_EXEC | _PAGE_WRITE) +#define PAGE_SHADOWSTACK __pgprot(_PAGE_BASE | _PAGE_WRITE) #define PAGE_COPY PAGE_READ #define PAGE_COPY_EXEC PAGE_READ_EXEC diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index d77afe05578f..43a448bf254b 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -7,6 +7,7 @@ #include #include +#include static long riscv_sys_mmap(unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, @@ -16,6 +17,15 @@ static long riscv_sys_mmap(unsigned long addr, unsigned long len, if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) return -EINVAL; + /* + * If PROT_WRITE is specified then extend that to PROT_READ + * protection_map[VM_WRITE] is now going to select shadow stack encodings. + * So specifying PROT_WRITE actually should select protection_map [VM_WRITE | VM_READ] + * If user wants to create shadow stack then they should use `map_shadow_stack` syscall. + */ + if (unlikely((prot & PROT_WRITE) && !(prot & PROT_READ))) + prot |= PROT_READ; + return ksys_mmap_pgoff(addr, len, prot, flags, fd, offset >> (PAGE_SHIFT - page_shift_offset)); } diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index ab475ec6ca42..78b27164bf83 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -375,7 +375,7 @@ pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); static const pgprot_t protection_map[16] = { [VM_NONE] = PAGE_NONE, [VM_READ] = PAGE_READ, - [VM_WRITE] = PAGE_COPY, + [VM_WRITE] = PAGE_SHADOWSTACK, [VM_WRITE | VM_READ] = PAGE_COPY, [VM_EXEC] = PAGE_EXEC, [VM_EXEC | VM_READ] = PAGE_READ_EXEC,