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Thu, 1 May 2025 16:02:27 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 23/23] iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support Date: Thu, 1 May 2025 16:01:29 -0700 Message-ID: <359be8b10c75d2831f557d21affbbd49148c88a2.1746139811.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A346:EE_|SJ0PR12MB6808:EE_ X-MS-Office365-Filtering-Correlation-Id: 61930f20-8d18-4b3f-8acd-08dd890447e1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: Gw6iOSThdzCv8cee7l1wNA5Oc9+7NHJFi9p54wSpjvAFhI5Z4h6bgD7elRhLoY+TupiM8Wurjja5zhT97r1HRPC1MjIJUYuYp+5HE7od9JnU+FHJcAxmbkIbb62UsWMazD//FxTMK+q+xIrSr9U31d+sWCMzzMg1jBs8c6ky3DLeFKDyBC1TpmIQchNds8uSXVPEBJ3yHvMDEwuifKcI65rKUCrckqo79IqWcSWckulZyLgpECY3wEOjLllnfpxUIlhlYEbk9CgUw91eyR+MtSaqcknZX3ZeClhS+LSeRJ4rbX7SlFdXXWWV8RZrrDy4h125SAmV+FyLcLGnTxSxowUekhmRxXGBHXYhyFaMzJkuwgEbjVczHPbhTF+3fAEvTGHQCPzWRYYzW+bd92aRhEOwIIUKZkI6Pc97OZ/68Ve19RYurLGRG5Ptz3R3Wtk9W4CleEI/vlarjYxNnTqR0wM5sBDvfw0UpTERRf4ISQx3fo29bhaz1psh5Q1viT1jdzSRkJKbaWEhJv4NS6TNPiMEKXJDV5QQ0y++nBImJK4W/p1J7f8HUB9impnC2Js2aKU0NnRH9CPZCpBNcVtQLXG4wlPfG5I/ZTnc1sRNbPiEjxMu+8Yc8bXfv9Paxy8E7P1DGzDxprggPdCcYG2irVkR88QGnG2JF0d5cXbWLqPJmXPIcAz6b+5zP15ApfyPxv78xJe/rgyA4Xz2fJjLNXEsHYszOxnGrUAdyBN2s+GH9c2QWoHB6p+kUmp6XgFPAW1nLBuSzPjNdSjD3WqWJkT/6zfb9sqbPrw/Msa5id6EHvra/lsiTXp59HjCnhxFOf24CAOBKC1EtRwS4OpbSSOKHMorZ1XC5aOk9MhC5AxlEcHfM1kx8Ktbtm4iP5QdiLjph5xTUEv1DlxtZmxk6ALEKX6TwX9n8EEjiyI4vdrpZO1yLqvgJ1tbADJ1VCU99tb5GfYWb47H7FWt6WLx9+pcprW9osp7A8gqMDdEirN5BVPwX1qQV8h/ZoeCv8UikeukMuO6dzRrsITKdr/YOAcGb1u6zKjgou+Fohynxq4BkrQ2AzOo3GxHqiboGmUyVTo4i0fVjKp9OH3LtJTH74anAsQmWfidzEJELmSh3T6jB72dgRE864F+8u0DFIysZhvK8womv80y86Kizy7+LySsKiVgHYp7xQe2j6TnwjntPCGp6aRDTcskoyIQ5DU+65szKHgma8Iwi/0v4IOfZjtBrpXRYKQXzj/rCgvqDO1f4pMv0rHjeXPLHauWpTVUm7F4TsRxAq++Utd2hUZ1jFr39qPkBhls9VDfuHQpcSUf91CFL0Pf3QP2x1KJKv4YAN4EpvqC/wW60Uh2jlUQ89UVsaq9CJbNOXf82pDu6mTfTvk/6CxichslfdMlwVVU6lYdcmkk4UiNzyMsZ+55p0RgPuHVsgeuhlqDiVk65pjnJC5D4zDZiufBC6zPCfM+3BimWU4O9MMhti5tE563Q60Kx5mjC9rRw2ueSbRjhj8au56/U8IM9zIkvvcsFH8E X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2025 23:02:43.4273 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61930f20-8d18-4b3f-8acd-08dd890447e1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A346.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6808 Add a new vEVENTQ type for VINTFs that are assigned to the user space. Simply report the two 64-bit LVCMDQ_ERR_MAPs register values. Reviewed-by: Alok Tiwari Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- include/uapi/linux/iommufd.h | 15 +++++++++++++ .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 22 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index e5400453a82e..6f269e3c48d5 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1114,10 +1114,12 @@ struct iommufd_vevent_header { * enum iommu_veventq_type - Virtual Event Queue Type * @IOMMU_VEVENTQ_TYPE_DEFAULT: Reserved for future use * @IOMMU_VEVENTQ_TYPE_ARM_SMMUV3: ARM SMMUv3 Virtual Event Queue + * @IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV Extension IRQ */ enum iommu_veventq_type { IOMMU_VEVENTQ_TYPE_DEFAULT = 0, IOMMU_VEVENTQ_TYPE_ARM_SMMUV3 = 1, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV = 2, }; /** @@ -1141,6 +1143,19 @@ struct iommu_vevent_arm_smmuv3 { __aligned_le64 evt[4]; }; +/** + * struct iommu_vevent_tegra241_cmdqv - Tegra241 CMDQV IRQ + * (IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV) + * @lvcmdq_err_map: 128-bit logical vcmdq error map, little-endian. + * (Refer to register LVCMDQ_ERR_MAPs per VINTF ) + * + * The 128-bit register value from HW exclusively reflect the error bits for a + * Virtual Interface represented by a vIOMMU object. Read and report directly. + */ +struct iommu_vevent_tegra241_cmdqv { + __aligned_le64 lvcmdq_err_map[2]; +}; + /** * struct iommu_veventq_alloc - ioctl(IOMMU_VEVENTQ_ALLOC) * @size: sizeof(struct iommu_veventq_alloc) diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index 6bbc85886f79..df0497d571a9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -292,6 +292,20 @@ static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) /* ISR Functions */ +static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) +{ + struct iommufd_viommu *viommu = &vintf->vsmmu.core; + struct iommu_vevent_tegra241_cmdqv vevent_data; + int i; + + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) + vevent_data.lvcmdq_err_map[i] = + readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + + iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + &vevent_data, sizeof(vevent_data)); +} + static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) { int i; @@ -337,6 +351,14 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) vintf_map &= ~BIT_ULL(0); } + /* Handle other user VINTFs and their LVCMDQs */ + while (vintf_map) { + unsigned long idx = __ffs64(vintf_map); + + tegra241_vintf_user_handle_error(cmdqv->vintfs[idx]); + vintf_map &= ~BIT_ULL(idx); + } + return IRQ_HANDLED; }