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Thu, 1 May 2025 16:02:13 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 17/23] iommu/arm-smmu-v3-iommufd: Add vsmmu_alloc impl op Date: Thu, 1 May 2025 16:01:23 -0700 Message-ID: <4998a6ad7fbdf813468751fee1113e2daa874551.1746139811.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|IA1PR12MB6307:EE_ X-MS-Office365-Filtering-Correlation-Id: a875b748-0cce-4ca9-00df-08dd8904400c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026|7416014; X-Microsoft-Antispam-Message-Info: vUv9G3UhkZsfefVUBbsAMIbNP5BLRpWmk3TIn3+ZoC1SPunkKKiZbcSJacaVk/pQhbYI1wuRwVcG6ZCCPDSDDYbq7acOF4ExhsY0LPQ294US6pAsElGOYrKA6i92FukRrSEUVz8xqsK5es0aY5ZVSGhI21iD+N6ajrKV/X1fiAwPRfPP8Gr2xaNLh6kftprSI66kH1d9xsOYCJKRz11gQK+dm6syGXEsE8N6o46sj25iGOdh2I5Ct/8pTVWC3kATYPeLPqkkR1zE9jGxnwC4VNIhVF3GnMUZUGibB37GATanWvNrOaNR3V9wVbUGf4EnoeCYdFDLgFznE9KFyzQDEk8dHVMN68XTWyaW4XsFp/p4SSNfRnh+u3LYogc46pD5MNBKOVXcWs6o7z3U5AetgXOiFjl0qp4H8SPCbrogKBlyQLtJs4zCS9X9m9bDNmV5liLlTW5ffztoEIN7+iY7YQFSS0EBkxFyaRNXntAOo+XR1M1Pcaayr9a6z+r8nQ8sNpgU2AwjLrxpueLD8olmup+RsAIpBld7pw/vq1qeH36nEuVHS1q4uixouTA9l9zNIWQy7BTFoMGcds1Y6xzUo021WgsLj0+wXW+oNV4r9/k9V50nnq+YgyHJ0qdk3g0pI+TyoW4HXFlsWr4FVvdf1sfsFIt5DriZvPuFhTHbaphR2FrDVUkMrm1a0KJvDCftTIhqr5FdQWbcP/krnqzvSeCtDClImqkI4/zEkpUErSJWqdhpkoK0HbeZ/oPRsXJ0Z9HwEJDvwHKQRTkmn9TcRClkeTj0mRC0I0CUxpS9ZFT4amhN8zR8AXuzD6xD9WgYgN9/XGBdyaPrFaybe+jfAuTzyPhTWumGdfmv03mxwbEPODAHMc2Dk7RWZZqkqVKeZM6caOksmsTV3YwaS/Wus3CjOIvukcQmwDRT16Ds7ezEXvm58MGhzRGgkcCn6wuEiVYa5ijxqMZ/HactKdOooYJpHzGqbKs3k1NLqvpO99maUvTle6x5vZ5Q0pGDQfnwKx3kJfW4re1UIYyerHcdMym8rBOEomuFi2hfTxW6hyuSHFi9xPdCbORcfSEfYM+mTchfihRxHq1a6elvuA8ca/cSn+bvXxXN1kI+n2iV5/vNu3lHsPgLP6niH0Py5KU5kDr+EQEphWxnYTgtUEWniS2D+FddLH6bnqhwRBwxZqiDEL+tUZ6g8Tbg8vRwEega/hMVUiwgtPmWp1SGlZTVnMt0haam23tlr0vypQOv60pcSFWt71t1tvOqKg1s1eZHUECTi3ZCzerz8WxRjFZumiK4AWjV8Pt4H6HV/a5NY60KDfMt7M6eVgp0UGiiGt4Neq86jiPdwA4OUvqJOKWIa/gkNecHKH8D7Y6HjEzAmqRX2J/1EA1kCHB2bbFOjr81vuARBGfDtA8wWeZD05ifpkAtBANzIQmj627Yj4dehF6x22+uLjdU6VBmTHI9KoSFKUZn7XmdP379h9UKuGo/4CAYC0itgeMnVSp+xR8PYcq2hnY8M4IcHOf4HcO9icmw X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2025 23:02:30.2380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a875b748-0cce-4ca9-00df-08dd8904400c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6307 An impl driver might want to allocate its own type of vIOMMU object or the standard IOMMU_VIOMMU_TYPE_ARM_SMMUV3 by setting up its own SW/HW bits, as the tegra241-cmdqv driver will add IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV. Add a vsmmu_alloc op and prioritize it in arm_vsmmu_alloc(). Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++++++ .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 17 +++++++++++------ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6b8f0d20dac3..a5835af72417 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -16,6 +16,7 @@ #include struct arm_smmu_device; +struct arm_smmu_domain; /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 @@ -720,6 +721,11 @@ struct arm_smmu_impl_ops { int (*init_structures)(struct arm_smmu_device *smmu); struct arm_smmu_cmdq *(*get_secondary_cmdq)( struct arm_smmu_device *smmu, struct arm_smmu_cmdq_ent *ent); + struct arm_vsmmu *(*vsmmu_alloc)( + struct arm_smmu_device *smmu, + struct arm_smmu_domain *smmu_domain, struct iommufd_ctx *ictx, + unsigned int viommu_type, + const struct iommu_user_data *user_data); }; /* An SMMUv3 instance */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 66855cae775e..b316d1df043f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -392,10 +392,7 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, iommu_get_iommu_dev(dev, struct arm_smmu_device, iommu); struct arm_smmu_master *master = dev_iommu_priv_get(dev); struct arm_smmu_domain *s2_parent = to_smmu_domain(parent); - struct arm_vsmmu *vsmmu; - - if (viommu_type != IOMMU_VIOMMU_TYPE_ARM_SMMUV3) - return ERR_PTR(-EOPNOTSUPP); + struct arm_vsmmu *vsmmu = ERR_PTR(-EOPNOTSUPP); if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) return ERR_PTR(-EOPNOTSUPP); @@ -423,8 +420,16 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, !(smmu->features & ARM_SMMU_FEAT_S2FWB)) return ERR_PTR(-EOPNOTSUPP); - vsmmu = iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, - &arm_vsmmu_ops); + /* Prioritize the impl that may support IOMMU_VIOMMU_TYPE_ARM_SMMUV3 */ + if (master->smmu->impl_ops && master->smmu->impl_ops->vsmmu_alloc) + vsmmu = master->smmu->impl_ops->vsmmu_alloc( + master->smmu, s2_parent, ictx, viommu_type, user_data); + if (PTR_ERR(vsmmu) == -EOPNOTSUPP) { + /* Otherwise, allocate an IOMMU_VIOMMU_TYPE_ARM_SMMUV3 here */ + if (viommu_type == IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + vsmmu = iommufd_viommu_alloc(ictx, struct arm_vsmmu, + core, &arm_vsmmu_ops); + } if (IS_ERR(vsmmu)) return ERR_CAST(vsmmu);