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Sat, 17 May 2025 20:22:17 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 13/29] iommufd/viommu: Introduce IOMMUFD_OBJ_HW_QUEUE and its related struct Date: Sat, 17 May 2025 20:21:30 -0700 Message-ID: <580a36f629402506d232052ddd20ef21ec91d5bc.1747537752.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017091:EE_|SN7PR12MB8146:EE_ X-MS-Office365-Filtering-Correlation-Id: 95c20839-d9fd-47bc-e85d-08dd95bb38f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|7416014|376014|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: YMuWDeQA89bdSgN2QC7DwXGSUdwcGbQw6GodtEqRm5fb4mjuGnkR9li+Hy88RP85EhTTyYr8umN3Y0OoXT72JhyEBhXLGolDOZ5rWH1mKX2PmzPR/xn58nErJrf+8SWRc9suj7xQNsw8QzemrQVaPjgcGwd3ID9grEe+4b2OJD1wMTqzQEakX0Sm3WlFsYSxPBOdHuywOt6h8Oepyi+Z72S67bf5SQVjHGKC6azESrXiUAGA5Pr6++vkhuETRL/RtxY3X2YTO18zXpMF71urq4jT/KGdDN94MZV4KtUp5b2o/cAZeEu7BYTddqDFKbHBJKqNGRXJPfz0tgTJM7CuJfW+L24dtptZlHGAKn7WdoWQnETK3R32N/64SUTf/QykXJ1Eh5AhO9Wvo5wt/wR/QsGgD2efX7il+CvSEcZC0iy/E4Fq+XTOBPNzT2+d1t8MP608+sXVtb3QUadmnJe9bT98SE/0LesNNg6Lh37GHLgpCv6otiLNeSKW1B0ruddlgGFyhtG0YwBqUi+HPUPnhFywXTiE9nBd74yjNy2Xzh6aLfj1LA5vdpmgepKlzvfs+sDiu7+vBpx+Bp2G6qfFwUdYCD+IgTx4zN59HkdaRAnppTLpiC87WEJ4nOqivltc2hfExyVml97OQVeBOjid9PPIPivaOO1YpXduAKWD9EVAh9lAJcs1K0KfuH8uS09CpyX9kECidpshGW/dAgU6mc7X2qCHJi26wrSA+jNSBlaOA3JYXfED1fWhYqlaU0lsB50AhPtSDagpq9aiQiWqjVMqhTxw7cDmDJHVvpAiw8HoQ3dvp4wWn4Ymx4t4tSN9DET8/Pki5VoJiUS8TE+tq5+QdPmCU/VJnHmZYUSLAvi4OpofDkBUljkFeoVWCPTDJi1wsqqj9kN8bMWnTkuiFewrZuzfOHSuDujYv1kqzOePqI7VEXChjBKNdB/YtG3sxCPXRrLth+5moIPMnyvDZF2P3vdlgNucs55ku7LWUI0zDWgQz1D/04ZF4xdJtSA8gHKHdHml5zVnsaOzAWBy0wd0jCs+JceLoiDiMNux2OJYSg0I0d6RR/mq6VZeIQl59BHWu1LRA7FOZObA+qGZ+8JaitxWbGztmyL7RgFDktSE/il+wFySC0PHtdIsrmHgXaWh+Y+FTNV/H1pcg4uEeQaD2PhG++3Nb1nopRAo060+z9yqOgV1PsmyvT4IiiA+wbY7fnnhep2As9FqEHwjcU7FaC3SJYJDDUL9LjiXErpBniWOAXrXUhMt1e42EGRoBnxea3swBlu1qKhbczDWMOu9QkVx96raVlxcq8DyDsZyJTtFZyF38GGKRXbJAN3dVwK2FxxbaE1KEiyOL7xNmKNkcpm+aUR+u5E5VS0vZKTghlyg528F7OhOnReYF9RnFL9akkW0s49EHQhAPA52y7IXe91lUKWzBQ5TQwz/H+Gm4BwNORHkocdKdbYRDFcX7Qmf4HfyAE0NPCFr8fsvxDiFd3mrdfAh0yL+BwuDBf+ghfY41TWpi3GQxkyC8mQz X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(7416014)(376014)(82310400026)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2025 03:22:30.2211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95c20839-d9fd-47bc-e85d-08dd95bb38f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017091.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8146 Add IOMMUFD_OBJ_HW_QUEUE with an iommufd_hw_queue structure, representing a HW-accelerated queue type of IOMMU's physical queue that can be passed through to a user space VM for direct hardware control, such as: - NVIDIA's Virtual Command Queue - AMD vIOMMU's Command Buffer, Event Log Buffer, and PPR Log Buffer Introduce an allocator iommufd_hw_queue_alloc(). And add a pair of viommu ops for iommufd to forward user space ioctls to IOMMU drivers. Given that the first user of this HW QUEUE (tegra241-cmdqv) will need to ensure the queue memory to be physically contiguous, add a flag property in iommufd_viommu_ops and IOMMUFD_VIOMMU_FLAG_HW_QUEUE_READS_PA to allow driver to flag it so that the core will validate the physical pages of a given guest queue. Reviewed-by: Lu Baolu Reviewed-by: Pranjal Shrivastava Reviewed-by: Vasant Hegde Signed-off-by: Nicolin Chen --- include/linux/iommufd.h | 47 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 266ac6805213..923c66ccc15a 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -38,6 +38,7 @@ enum iommufd_object_type { IOMMUFD_OBJ_VIOMMU, IOMMUFD_OBJ_VDEVICE, IOMMUFD_OBJ_VEVENTQ, + IOMMUFD_OBJ_HW_QUEUE, #ifdef CONFIG_IOMMUFD_TEST IOMMUFD_OBJ_SELFTEST, #endif @@ -133,6 +134,24 @@ struct iommufd_vdevice { u64 id; /* per-vIOMMU virtual ID */ }; +struct iommufd_hw_queue { + struct iommufd_object obj; + struct iommufd_ctx *ictx; + struct iommufd_viommu *viommu; + u64 base_addr; /* in guest physical address space */ + size_t length; +}; + +enum iommufd_viommu_flags { + /* + * The HW does not go through an address translation table but reads the + * physical address space directly: iommufd core should pin the physical + * pages backing the queue memory that's allocated for the HW QUEUE, and + * ensure those physical pages are contiguous in the physical space. + */ + IOMMUFD_VIOMMU_FLAG_HW_QUEUE_READS_PA = 1 << 0, +}; + /** * struct iommufd_viommu_ops - vIOMMU specific operations * @destroy: Clean up all driver-specific parts of an iommufd_viommu. The memory @@ -158,8 +177,18 @@ struct iommufd_vdevice { * @vdevice_destroy: Clean up all driver-specific parts of an iommufd_vdevice. * The memory of the vDEVICE will be free-ed by iommufd core * after calling this op + * @hw_queue_alloc: Allocate a HW QUEUE object for a HW-accelerated queue given + * the @type (must be defined in include/uapi/linux/iommufd.h) + * for the @viommu. @index carries the logical HW QUEUE ID per + * @viommu in a guest VM, for a multi-queue model; @base_addr + * carries the guest physical base address of the queue memory; + * @length carries the size of the queue + * @hw_queue_destroy: Clean up all driver-specific parts of an iommufd_hw_queue. + * The memory of the HW QUEUE will be free-ed by iommufd core + * after calling this op */ struct iommufd_viommu_ops { + u32 flags; void (*destroy)(struct iommufd_viommu *viommu); struct iommu_domain *(*alloc_domain_nested)( struct iommufd_viommu *viommu, u32 flags, @@ -171,6 +200,10 @@ struct iommufd_viommu_ops { struct device *dev, u64 virt_id); void (*vdevice_destroy)(struct iommufd_vdevice *vdev); + struct iommufd_hw_queue *(*hw_queue_alloc)( + struct iommufd_ucmd *ucmd, struct iommufd_viommu *viommu, + unsigned int type, u32 index, u64 base_addr, size_t length); + void (*hw_queue_destroy)(struct iommufd_hw_queue *hw_queue); }; #if IS_ENABLED(CONFIG_IOMMUFD) @@ -312,4 +345,18 @@ static inline int iommufd_viommu_report_event(struct iommufd_viommu *viommu, } \ ret; \ }) + +#define iommufd_hw_queue_alloc(ucmd, viommu, drv_struct, member) \ + ({ \ + drv_struct *ret; \ + \ + static_assert(__same_type(struct iommufd_viommu, *viommu)); \ + ret = (drv_struct *)__iommufd_object_alloc_ucmd( \ + ucmd, ret, IOMMUFD_OBJ_HW_QUEUE, member.obj); \ + if (!IS_ERR(ret)) { \ + ret->member.viommu = viommu; \ + ret->member.ictx = viommu->ictx; \ + } \ + ret; \ + }) #endif