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Thu, 1 May 2025 16:02:15 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 18/23] iommu/arm-smmu-v3-iommufd: Support implementation-defined hw_info Date: Thu, 1 May 2025 16:01:24 -0700 Message-ID: <73d0c6790c1b1c6871041745e238fd08c33c4f2a.1746139811.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|CH2PR12MB4070:EE_ X-MS-Office365-Filtering-Correlation-Id: ff27957f-6878-4e99-29ac-08dd89043f6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: pTDn2yp4BgOzVaBLyqqIJIjkkYKsardUipYbadLEq6ayIbqaybcJoEyaPObCnxnlUstcTJwtt64gMck8Ck4zX/YKLS+xJ2jcSbX1tXAXIcSPvXaJ246DIrMnWMdO+KMtZPTfj8KpkYTrugCPZGQJQWlCmvE6raU3jRimIegdQShrS6c8Q/Oos8DCwQCErJKnTsBGqxxTPTyts+1ZZUBQyUZtPd7yWn4syqHJ919lsGX6JY4f86YInlCCefCXEUqlERNJVAfpb+lhItmE0c0g1td/kka1H2r1b1/RAZPbAb3qeLJ99Y/wscbUj6B3/5e3ILUa34hP2Bedm+mEBlTvedsT4+qtJCq3dTJYcgcDVcKPzjrGv6/jmxmQYOg01tR2lI/NKisDGQlLcMTDkAM9hckOJ6tcTTbZLoj+1cFopJQQCoWbxF2+p72OHMGNRZlJ16gbL/PeiR1/0/06At9llQ7uAqRZaGp0ajkCICpXorj1G3xPWsAMoQo8CTC2Q8S5nI/goX+DEYqlwsPqYcrydPqRl32n27wRruhruWcMQoixEgV4D78tHO25qrgG2Ney3WeKYM1OgQF60tizZk4yffMf3Hw3R/a0dqPnJj7CYnFvJqpc0yQXAIsNRsj5ZwluoUuIrINNMVZnChDysx7Z9/5SoTl/PxQgnOsIHKEfyW/jgMmnHdBrnPz38s/nVRdI0i/fwdnJem9B51BZ82rPh/vEMU4Chgqya+3iuZ1TBU2yiNLrlzPCeAf59tvkRqmMthLvKMnHaa8IxGCCgdTq8F+SxdJVomlRaA68fi5MKaiujbA5gN/7SB/QD3DYVCSM1rdNdYEFYeVaauXxooCMAjrkGgGsPgmQjhx2ddi1z2GMKguHMN9oRuTfWfAiiVwEd9cF2KJXD5uu2ufoLJmPdU5CsDN3hWq1n2whtQ6N2AABL9K/iIq1w08ypEYgo+GPSFcSew46j/IcON4/nZb8Ned975V/a17kEOk/YeuWG/yfBoxEL00+/uuL20EqxbSAiyuIxpKVRKgpPke8U3Nba1FxasshXTgP4BU7JnI2wn7f4cPFVnZUm7Q6SBBAPnZS/Vpz+ImKEASoIVmQufwq7pMEu3wnfOULBG/bLbCjLgi//t9UE1IsKvj208Drv0cSpHoYmJw6Jf+JLxrecD6bzaENe7t5ADmbJXihZ/FpCz2Ircr9eRqs+N9laatHZ9uK8nToVFLeCvKXcz9yOTwcojhBMBYSW8gxM83DP35aWTZvHIeoqs0pXgi0MdGT66kNDPhIUXnCGWYZ7vWP2QhfbGYSaJxp8HE9KQUirAQxCjjk2KCUHlqkuibeI0fc7KVTKUiBgIeEVpqYTy6BJWFvCTHZ3bgHgkO9tNtzWgv/epUp+IpT8jm+bhLt28d/ywUjvOyCvke+lPK541BXwVqnPKCyUbwCUaQ2ZAufrRnaOblft6pRU5REb+DzSARHon0gcaHsCt2TCQtysEmiATEt8iK8Uw0QqNANr0fmnhKNO89bymgpi2/m+XRdN6fHLSVs X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2025 23:02:29.2330 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff27957f-6878-4e99-29ac-08dd89043f6f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4070 Repurpose the @__reserved field in the struct iommu_hw_info_arm_smmuv3, to an HW implementation-defined field @impl. This will be used by Tegra241 CMDQV implementation on top of a standard ARM SMMUv3 IOMMU. The @impl will be only valid if @flags is set with an implementation-defined flag. Thus in the driver-level, add an hw_info impl op that will return such a flag and fill the impl field. Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + include/uapi/linux/iommufd.h | 4 ++-- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 16 +++++++++++++--- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index a5835af72417..bab7a9ce1283 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -726,6 +726,7 @@ struct arm_smmu_impl_ops { struct arm_smmu_domain *smmu_domain, struct iommufd_ctx *ictx, unsigned int viommu_type, const struct iommu_user_data *user_data); + u32 (*hw_info)(struct arm_smmu_device *smmu, u32 *impl); }; /* An SMMUv3 instance */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index c6742bb00a41..fd9089bfea01 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -554,7 +554,7 @@ struct iommu_hw_info_vtd { * (IOMMU_HW_INFO_TYPE_ARM_SMMUV3) * * @flags: Must be set to 0 - * @__reserved: Must be 0 + * @impl: Must be 0 * @idr: Implemented features for ARM SMMU Non-secure programming interface * @iidr: Information about the implementation and implementer of ARM SMMU, * and architecture version supported @@ -585,7 +585,7 @@ struct iommu_hw_info_vtd { */ struct iommu_hw_info_arm_smmuv3 { __u32 flags; - __u32 __reserved; + __u32 impl; __u32 idr[6]; __u32 iidr; __u32 aidr; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index b316d1df043f..f8bf89a80eb6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -10,7 +10,9 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type) { struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_device *smmu = master->smmu; struct iommu_hw_info_arm_smmuv3 *info; + u32 flags = 0, impl = 0; u32 __iomem *base_idr; unsigned int i; @@ -18,15 +20,23 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type) if (!info) return ERR_PTR(-ENOMEM); - base_idr = master->smmu->base + ARM_SMMU_IDR0; + base_idr = smmu->base + ARM_SMMU_IDR0; for (i = 0; i <= 5; i++) info->idr[i] = readl_relaxed(base_idr + i); - info->iidr = readl_relaxed(master->smmu->base + ARM_SMMU_IIDR); - info->aidr = readl_relaxed(master->smmu->base + ARM_SMMU_AIDR); + info->iidr = readl_relaxed(smmu->base + ARM_SMMU_IIDR); + info->aidr = readl_relaxed(smmu->base + ARM_SMMU_AIDR); *length = sizeof(*info); *type = IOMMU_HW_INFO_TYPE_ARM_SMMUV3; + if (smmu->impl_ops && smmu->impl_ops->hw_info) { + flags = smmu->impl_ops->hw_info(smmu, &impl); + if (flags) { + info->impl = impl; + info->flags |= flags; + } + } + return info; }